Update from 2013.01 to 2013.07

[karo-tx-uboot.git] / arch / arm / include / asm / arch-mxs / regs-lcdif.h

diff --git a/arch/arm/include/asm/arch-mxs/regs-lcdif.h b/arch/arm/include/asm/arch-mxs/regs-lcdif.h
index 10b33dd4d90c81f5e26a9973477a45fc79fcfdcb..a845883911b02204ad7d5f16613d0e1a296ad4d8 100644 (file)
--- a/arch/arm/include/asm/arch-mxs/regs-lcdif.h
+++ b/arch/arm/include/asm/arch-mxs/regs-lcdif.h
@@ -7,61 +7,61 @@
  * Based on code from LTIB:
  * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- *
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __MX28_REGS_LCDIF_H__
 #define __MX28_REGS_LCDIF_H__
 
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
 
 #ifndef        __ASSEMBLY__
 struct mxs_lcdif_regs {
-       mxs_reg_32(hw_lcdif_ctrl)               /* 0x00 */
-       mxs_reg_32(hw_lcdif_ctrl1)              /* 0x10 */
+       mxs_reg_32(hw_lcdif_ctrl);              /* 0x00 */
+       mxs_reg_32(hw_lcdif_ctrl1);             /* 0x10 */
+#if defined(CONFIG_MX28)
        mxs_reg_32(hw_lcdif_ctrl2)              /* 0x20 */
-       mxs_reg_32(hw_lcdif_transfer_count)     /* 0x30 */
-       mxs_reg_32(hw_lcdif_cur_buf)            /* 0x40 */
-       mxs_reg_32(hw_lcdif_next_buf)           /* 0x50 */
-       mxs_reg_32(hw_lcdif_timing)             /* 0x60 */
-       mxs_reg_32(hw_lcdif_vdctrl0)            /* 0x70 */
-       mxs_reg_32(hw_lcdif_vdctrl1)            /* 0x80 */
-       mxs_reg_32(hw_lcdif_vdctrl2)            /* 0x90 */
-       mxs_reg_32(hw_lcdif_vdctrl3)            /* 0xa0 */
-       mxs_reg_32(hw_lcdif_vdctrl4)            /* 0xb0 */
-       mxs_reg_32(hw_lcdif_dvictrl0)           /* 0xc0 */
-       mxs_reg_32(hw_lcdif_dvictrl1)           /* 0xd0 */
-       mxs_reg_32(hw_lcdif_dvictrl2)           /* 0xe0 */
-       mxs_reg_32(hw_lcdif_dvictrl3)           /* 0xf0 */
-       mxs_reg_32(hw_lcdif_dvictrl4)           /* 0x100 */
-       mxs_reg_32(hw_lcdif_csc_coeffctrl0)     /* 0x110 */
-       mxs_reg_32(hw_lcdif_csc_coeffctrl1)     /* 0x120 */
-       mxs_reg_32(hw_lcdif_csc_coeffctrl2)     /* 0x130 */
-       mxs_reg_32(hw_lcdif_csc_coeffctrl3)     /* 0x140 */
-       mxs_reg_32(hw_lcdif_csc_coeffctrl4)     /* 0x150 */
-       mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */
-       mxs_reg_32(hw_lcdif_csc_limit)          /* 0x170 */
-       mxs_reg_32(hw_lcdif_data)               /* 0x180 */
-       mxs_reg_32(hw_lcdif_bm_error_stat)      /* 0x190 */
-       mxs_reg_32(hw_lcdif_crc_stat)           /* 0x1a0 */
-       mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1b0 */
-       mxs_reg_32(hw_lcdif_version)            /* 0x1c0 */
-       mxs_reg_32(hw_lcdif_debug0)             /* 0x1d0 */
-       mxs_reg_32(hw_lcdif_debug1)             /* 0x1e0 */
-       mxs_reg_32(hw_lcdif_debug2)             /* 0x1f0 */
+#endif                                         /* MX23/MX28 */
+       mxs_reg_32(hw_lcdif_transfer_count);    /* 0x20/0x30 */
+       mxs_reg_32(hw_lcdif_cur_buf);           /* 0x30/0x40 */
+       mxs_reg_32(hw_lcdif_next_buf);          /* 0x40/0x50 */
+
+#if defined(CONFIG_MX23)
+       reg_32(reserved1);                      /* 0x50 */
+#endif
+
+       mxs_reg_32(hw_lcdif_timing);            /* 0x60 */
+       mxs_reg_32(hw_lcdif_vdctrl0);           /* 0x70 */
+       mxs_reg_32(hw_lcdif_vdctrl1);           /* 0x80 */
+       mxs_reg_32(hw_lcdif_vdctrl2);           /* 0x90 */
+       mxs_reg_32(hw_lcdif_vdctrl3);           /* 0xa0 */
+       mxs_reg_32(hw_lcdif_vdctrl4);           /* 0xb0 */
+       mxs_reg_32(hw_lcdif_dvictrl0);          /* 0xc0 */
+       mxs_reg_32(hw_lcdif_dvictrl1);          /* 0xd0 */
+       mxs_reg_32(hw_lcdif_dvictrl2);          /* 0xe0 */
+       mxs_reg_32(hw_lcdif_dvictrl3);          /* 0xf0 */
+       mxs_reg_32(hw_lcdif_dvictrl4);          /* 0x100 */
+       mxs_reg_32(hw_lcdif_csc_coeffctrl0);    /* 0x110 */
+       mxs_reg_32(hw_lcdif_csc_coeffctrl1);    /* 0x120 */
+       mxs_reg_32(hw_lcdif_csc_coeffctrl2);    /* 0x130 */
+       mxs_reg_32(hw_lcdif_csc_coeffctrl3);    /* 0x140 */
+       mxs_reg_32(hw_lcdif_csc_coeffctrl4);    /* 0x150 */
+       mxs_reg_32(hw_lcdif_csc_offset);        /* 0x160 */
+       mxs_reg_32(hw_lcdif_csc_limit);         /* 0x170 */
+
+#if defined(CONFIG_MX23)
+       reg_32(reserved2[3]);                   /* 0x180-0x1a0 */
+#endif                                         /*  MX23/MX28 */
+       mxs_reg_32(hw_lcdif_data)               /* 0x1b0/0x180 */
+       mxs_reg_32(hw_lcdif_bm_error_stat)      /* 0x1c0/0x190 */
+#if defined(CONFIG_MX28)
+       mxs_reg_32(hw_lcdif_crc_stat)           /*       0x1a0 */
+#endif
+       mxs_reg_32(hw_lcdif_lcdif_stat);        /* 0x1d0/0x1b0 */
+       mxs_reg_32(hw_lcdif_version);           /* 0x1e0/0x1c0 */
+       mxs_reg_32(hw_lcdif_debug0);            /* 0x1f0/0x1d0 */
+       mxs_reg_32(hw_lcdif_debug1);            /* 0x200/0x1e0 */
+       mxs_reg_32(hw_lcdif_debug2);            /*       0x1f0 */
 };
 #endif
 
@@ -201,8 +201,13 @@ struct mxs_lcdif_regs {
 #define        LCDIF_VDCTRL1_VSYNC_PERIOD(n)                           (((n) << LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET) & \
                                                LCDIF_VDCTRL1_VSYNC_PERIOD_MASK)
 
+#if defined(CONFIG_MX23)
+#define        LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK                    (0xff << 24)
+#define        LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET                  24
+#elif defined(CONFIG_MX28)
 #define        LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK                    (0x3fff << 18)
 #define        LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET                  18
+#endif
 #define        LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(n)                      (((n) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) & \
                                                LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK)
 #define        LCDIF_VDCTRL2_HSYNC_PERIOD_MASK                         0x3ffff