sunxi: nand: Add pinmux and clock settings for NAND support

[karo-tx-uboot.git] / arch / arm / include / asm / arch-sunxi / gpio.h

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 437dd35b68d47844b8c7d05cad65ed13478ddb0c..8382101558c8ddaffabdff1e0d602d6e5eaba00d 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -45,9 +45,13 @@
  *
  * sun8i has 1 bank:
  * PL0 - PL11
+ *
+ * sun9i has 3 banks:
+ * PL0 - PL9  | PM0 - PM15  | PN0 - PN1
  */
 #define SUNXI_GPIO_L   11
 #define SUNXI_GPIO_M   12
+#define SUNXI_GPIO_N   13
 
 struct sunxi_gpio {
        u32 cfg[4];
@@ -80,7 +84,7 @@ struct sunxi_gpio_reg {
 #define GPIO_CFG_INDEX(pin)    (((pin) & 0x1f) >> 3)
 #define GPIO_CFG_OFFSET(pin)   ((((pin) & 0x1f) & 0x7) << 2)
 
-#define GPIO_DRV_INDEX(pin)   (((pin) & 0x1f) >> 4)
+#define GPIO_DRV_INDEX(pin)    (((pin) & 0x1f) >> 4)
 #define GPIO_DRV_OFFSET(pin)   ((((pin) & 0x1f) & 0xf) << 1)
 
 #define GPIO_PULL_INDEX(pin)   (((pin) & 0x1f) >> 4)
@@ -114,6 +118,8 @@ enum sunxi_gpio_number {
        SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H),
        SUNXI_GPIO_L_START = 352,
        SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L),
+       SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M),
+       SUNXI_GPIO_AXP0_START = 1024,
 };
 
 /* SUNXI GPIO number definitions */
@@ -128,65 +134,98 @@ enum sunxi_gpio_number {
 #define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr))
 #define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr))
 #define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr))
+#define SUNXI_GPN(_nr) (SUNXI_GPIO_N_START + (_nr))
+
+#define SUNXI_GPAXP0(_nr)      (SUNXI_GPIO_AXP0_START + (_nr))
 
 /* GPIO pin function config */
 #define SUNXI_GPIO_INPUT       0
 #define SUNXI_GPIO_OUTPUT      1
 
-#define SUNXI_GPA0_EMAC                2
-#define SUN7I_GPA0_GMAC                5
-
-#define SUNXI_GPB0_TWI0                2
-
-#define SUN4I_GPB22_UART0_TX   2
-#define SUN4I_GPB23_UART0_RX   2
-
-#define SUN5I_GPB19_UART0_TX   2
-#define SUN5I_GPB20_UART0_RX   2
-
-#define SUN5I_GPG3_SDC1                2
-
-#define SUN5I_GPG3_UART1_TX    4
-#define SUN5I_GPG4_UART1_RX    4
-
-#define SUNXI_GPC6_SDC2                3
-
-#define SUNXI_GPF0_SDC0                2
-
-#define SUNXI_GPF2_SDC0                2
-
-#ifdef CONFIG_MACH_SUN8I
-#define SUNXI_GPF2_UART0_TX    3
-#define SUNXI_GPF4_UART0_RX    3
-#else
-#define SUNXI_GPF2_UART0_TX    4
-#define SUNXI_GPF4_UART0_RX    4
-#endif
-
-#define SUN4I_GPG0_SDC1                4
-
-#define SUN4I_GPH22_SDC1       5
-
-#define SUN6I_GPH20_UART0_TX   2
-#define SUN6I_GPH21_UART0_RX   2
-
-#define SUN4I_GPI4_SDC3                2
-
-#define SUN8I_GPL2_R_UART_TX   2
-#define SUN8I_GPL3_R_UART_RX   2
+#define SUNXI_GPA_EMAC         2
+#define SUN6I_GPA_GMAC         2
+#define SUN7I_GPA_GMAC         5
+#define SUN6I_GPA_SDC2         5
+#define SUN6I_GPA_SDC3         4
+
+#define SUN4I_GPB_TWI0         2
+#define SUN4I_GPB_TWI1         2
+#define SUN5I_GPB_TWI1         2
+#define SUN4I_GPB_TWI2         2
+#define SUN5I_GPB_TWI2         2
+#define SUN4I_GPB_UART0                2
+#define SUN5I_GPB_UART0                2
+#define SUN8I_GPB_UART2                2
+#define SUN8I_A33_GPB_UART0    3
+
+#define SUNXI_GPC_NAND         2
+#define SUNXI_GPC_SDC2         3
+#define SUN6I_GPC_SDC3         4
+
+#define SUN8I_GPD_SDC1         3
+#define SUNXI_GPD_LCD0         2
+#define SUNXI_GPD_LVDS0                3
+
+#define SUN5I_GPE_SDC2         3
+#define SUN8I_GPE_TWI2         3
+
+#define SUNXI_GPF_SDC0         2
+#define SUNXI_GPF_UART0                4
+#define SUN8I_GPF_UART0                3
+
+#define SUN4I_GPG_SDC1         4
+#define SUN5I_GPG_SDC1         2
+#define SUN6I_GPG_SDC1         2
+#define SUN8I_GPG_SDC1         2
+#define SUN6I_GPG_TWI3         2
+#define SUN5I_GPG_UART1                4
+
+#define SUN4I_GPH_SDC1         5
+#define SUN6I_GPH_TWI0         2
+#define SUN8I_GPH_TWI0         2
+#define SUN6I_GPH_TWI1         2
+#define SUN8I_GPH_TWI1         2
+#define SUN6I_GPH_TWI2         2
+#define SUN6I_GPH_UART0                2
+#define SUN9I_GPH_UART0                2
+
+#define SUNXI_GPI_SDC3         2
+#define SUN7I_GPI_TWI3         3
+#define SUN7I_GPI_TWI4         3
+
+#define SUN6I_GPL0_R_P2WI_SCK  3
+#define SUN6I_GPL1_R_P2WI_SDA  3
+
+#define SUN8I_GPL_R_RSB                2
+#define SUN8I_GPL_R_UART       2
+
+#define SUN9I_GPN_R_RSB                3
 
 /* GPIO pin pull-up/down config */
 #define SUNXI_GPIO_PULL_DISABLE        0
 #define SUNXI_GPIO_PULL_UP     1
 #define SUNXI_GPIO_PULL_DOWN   2
 
+/* Virtual AXP0 GPIOs */
+#define SUNXI_GPIO_AXP0_PREFIX "AXP0-"
+#define SUNXI_GPIO_AXP0_VBUS_DETECT    4
+#define SUNXI_GPIO_AXP0_VBUS_ENABLE    5
+#define SUNXI_GPIO_AXP0_GPIO_COUNT     6
+
 void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val);
 void sunxi_gpio_set_cfgpin(u32 pin, u32 val);
 int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset);
 int sunxi_gpio_get_cfgpin(u32 pin);
 int sunxi_gpio_set_drv(u32 pin, u32 val);
 int sunxi_gpio_set_pull(u32 pin, u32 val);
+int sunxi_name_to_gpio_bank(const char *name);
 int sunxi_name_to_gpio(const char *name);
 #define name_to_gpio(name) sunxi_name_to_gpio(name)
 
+#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO
+int axp_gpio_init(void);
+#else
+static inline int axp_gpio_init(void) { return 0; }
+#endif
+
 #endif /* _SUNXI_GPIO_H */