Merge branch 'master' of git://git.denx.de/u-boot-spi

[karo-tx-uboot.git] / arch / arm / include / asm / arch-tegra / clock.h

diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h
index c3174bd7fce62e03700f464c2aef50fdb366a975..9d8114c4ecfaf87e4c6bf5c6910fffe92ce35af0 100644 (file)
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -20,6 +20,21 @@ enum clock_osc_freq {
        CLOCK_OSC_FREQ_COUNT,
 };
 
+/*
+ * Note that no Tegra clock register actually uses all of bits 31:28 as
+ * the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in
+ * those cases, nothing is stored in the bits about the mux field, so it's
+ * safe to pretend that the mux field extends all the way to the end of the
+ * register. As such, the U-Boot clock driver is currently a bit lazy, and
+ * doesn't distinguish between 31:28, 30:28, 29:28 and 28; it just lumps
+ * them all together and pretends they're all 31:28.
+ */
+enum {
+       MASK_BITS_31_30,
+       MASK_BITS_31_29,
+       MASK_BITS_31_28,
+};
+
 #include <asm/arch/clock-tables.h>
 /* PLL stabilization delay in usec */
 #define CLOCK_PLL_STABLE_DELAY_US 300
@@ -113,9 +128,9 @@ void reset_set_enable(enum periph_id periph_id, int enable);
 enum crc_reset_id {
        /* Things we can hold in reset for each CPU */
        crc_rst_cpu = 1,
-       crc_rst_de = 1 << 2,    /* What is de? */
-       crc_rst_watchdog = 1 << 3,
-       crc_rst_debug = 1 << 4,
+       crc_rst_de = 1 << 4,    /* What is de? */
+       crc_rst_watchdog = 1 << 8,
+       crc_rst_debug = 1 << 12,
 };
 
 /**
@@ -305,4 +320,6 @@ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon);
 /* SoC-specific TSC init */
 void arch_timer_init(void);
 
+void tegra30_set_up_pllp(void);
+
 #endif  /* _TEGRA_CLOCK_H_ */