Merge branch 'master' of git://git.denx.de/u-boot-arc

[karo-tx-uboot.git] / arch / arm / include / asm / arch-vf610 / crm_regs.h

diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h
index e17c7d1f7042f138ac41acb48eb100ebd02953e5..724682c683c70d1f94b0d6c43e005bd63215a12a 100644 (file)
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -150,17 +150,38 @@ struct anadig_reg {
 #define CCM_CACRR_ARM_CLK_DIV_MASK             0x7
 #define CCM_CACRR_ARM_CLK_DIV(v)               ((v) & 0x7)
 
+#define CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET                22
+#define CCM_CSCMR1_QSPI0_CLK_SEL_MASK          (0x3 << 22)
+#define CCM_CSCMR1_QSPI0_CLK_SEL(v)            (((v) & 0x3) << 22)
 #define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET       18
 #define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK         (0x3 << 18)
 #define CCM_CSCMR1_ESDHC1_CLK_SEL(v)           (((v) & 0x3) << 18)
+#define CCM_CSCMR1_NFC_CLK_SEL_OFFSET          12
+#define CCM_CSCMR1_NFC_CLK_SEL_MASK            (0x3 << 12)
+#define CCM_CSCMR1_NFC_CLK_SEL(v)              (((v) & 0x3) << 12)
 
 #define CCM_CSCDR1_RMII_CLK_EN                 (1 << 24)
 
+#define CCM_CSCDR2_NFC_EN                      (1 << 9)
+#define CCM_CSCDR2_NFC_FRAC_DIV_EN             (1 << 13)
+#define CCM_CSCDR2_NFC_CLK_INV                 (1 << 14)
+#define CCM_CSCDR2_NFC_FRAC_DIV_OFFSET         4
+#define CCM_CSCDR2_NFC_FRAC_DIV_MASK           (0xf << 4)
+#define CCM_CSCDR2_NFC_FRAC_DIV(v)             (((v) & 0xf) << 4)
+
 #define CCM_CSCDR2_ESDHC1_EN                   (1 << 29)
 #define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET       20
 #define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK         (0xf << 20)
 #define CCM_CSCDR2_ESDHC1_CLK_DIV(v)           (((v) & 0xf) << 20)
 
+#define CCM_CSCDR3_NFC_PRE_DIV_OFFSET          13
+#define CCM_CSCDR3_NFC_PRE_DIV_MASK            (0x7 << 13)
+#define CCM_CSCDR3_NFC_PRE_DIV(v)              (((v) & 0x7) << 13)
+#define CCM_CSCDR3_QSPI0_EN                    (1 << 4)
+#define CCM_CSCDR3_QSPI0_DIV(v)                        ((v) << 3)
+#define CCM_CSCDR3_QSPI0_X2_DIV(v)             ((v) << 2)
+#define CCM_CSCDR3_QSPI0_X4_DIV(v)             ((v) & 0x3)
+
 #define CCM_CSCMR2_RMII_CLK_SEL_OFFSET         4
 #define CCM_CSCMR2_RMII_CLK_SEL_MASK           (0x3 << 4)
 #define CCM_CSCMR2_RMII_CLK_SEL(v)             (((v) & 0x3) << 4)
@@ -170,6 +191,7 @@ struct anadig_reg {
 #define CCM_CCGR0_UART1_CTRL_MASK              (0x3 << 16)
 #define CCM_CCGR1_PIT_CTRL_MASK                        (0x3 << 14)
 #define CCM_CCGR1_WDOGA5_CTRL_MASK             (0x3 << 28)
+#define CCM_CCGR2_QSPI0_CTRL_MASK              (0x3 << 8)
 #define CCM_CCGR2_IOMUXC_CTRL_MASK             (0x3 << 16)
 #define CCM_CCGR2_PORTA_CTRL_MASK              (0x3 << 18)
 #define CCM_CCGR2_PORTB_CTRL_MASK              (0x3 << 20)
@@ -186,6 +208,7 @@ struct anadig_reg {
 #define CCM_CCGR7_SDHC1_CTRL_MASK              (0x3 << 4)
 #define CCM_CCGR9_FEC0_CTRL_MASK               0x3
 #define CCM_CCGR9_FEC1_CTRL_MASK               (0x3 << 2)
+#define CCM_CCGR10_NFC_CTRL_MASK               0x3
 
 #define ANADIG_PLL5_CTRL_BYPASS                 (1 << 16)
 #define ANADIG_PLL5_CTRL_ENABLE                 (1 << 13)