Merge branch 'master' of git://www.denx.de/git/u-boot-imx

[karo-tx-uboot.git] / arch / arm / include / asm / emif.h

diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index 9d72fe34fc71bc3ccf97176e5aac16450f553053..2fe5776c6cf390777f55c632068723e64d44034b 100644 (file)
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -14,11 +14,15 @@
 #define _EMIF_H_
 #include <asm/types.h>
 #include <common.h>
+#include <asm/io.h>
 
 /* Base address */
 #define EMIF1_BASE                             0x4c000000
 #define EMIF2_BASE                             0x4d000000
 
+#define EMIF_4D                                        0x4
+#define EMIF_4D5                               0x5
+
 /* Registers shifts, masks and values */
 
 /* EMIF_MOD_ID_REV */
@@ -581,7 +585,6 @@
        (0xFF << EMIF_SYS_ADDR_SHIFT))
 
 #define EMIF_EXT_PHY_CTRL_TIMING_REG   0x5
-#define EMIF_EXT_PHY_CTRL_CONST_REG    0x13
 
 /* Reg mapping structure */
 struct emif_reg_struct {
@@ -639,9 +642,16 @@ struct emif_reg_struct {
        u32 emif_ddr_phy_ctrl_1;
        u32 emif_ddr_phy_ctrl_1_shdw;
        u32 emif_ddr_phy_ctrl_2;
-       u32 padding7[12];
+       u32 padding7[4];
+       u32 emif_prio_class_serv_map;
+       u32 emif_connect_id_serv_1_map;
+       u32 emif_connect_id_serv_2_map;
+       u32 padding8[5];
        u32 emif_rd_wr_exec_thresh;
-       u32 padding8[55];
+       u32 emif_cos_config;
+       u32 padding9[6];
+       u32 emif_ddr_phy_status[21];
+       u32 padding10[27];
        u32 emif_ddr_ext_phy_ctrl_1;
        u32 emif_ddr_ext_phy_ctrl_1_shdw;
        u32 emif_ddr_ext_phy_ctrl_2;
@@ -690,6 +700,9 @@ struct emif_reg_struct {
        u32 emif_ddr_ext_phy_ctrl_23_shdw;
        u32 emif_ddr_ext_phy_ctrl_24;
        u32 emif_ddr_ext_phy_ctrl_24_shdw;
+       u32 padding[22];
+       u32 emif_ddr_fifo_misaligned_clear_1;
+       u32 emif_ddr_fifo_misaligned_clear_2;
 };
 
 struct dmm_lisa_map_regs {
@@ -697,6 +710,7 @@ struct dmm_lisa_map_regs {
        u32 dmm_lisa_map_1;
        u32 dmm_lisa_map_2;
        u32 dmm_lisa_map_3;
+       u8 is_ma_present;
 };
 
 #define CS0    0
@@ -854,20 +868,16 @@ struct dmm_lisa_map_regs {
 #define DPD_ENABLE     1
 
 /* Maximum delay before Low Power Modes */
-#ifndef CONFIG_OMAP54XX
-#define REG_CS_TIM             0xF
-#else
 #define REG_CS_TIM             0x0
-#endif
-#define REG_SR_TIM             0xF
-#define REG_PD_TIM             0xF
+#define REG_SR_TIM             0x0
+#define REG_PD_TIM             0x0
+
 
 /* EMIF_PWR_MGMT_CTRL register */
 #define EMIF_PWR_MGMT_CTRL (\
        ((REG_CS_TIM << EMIF_REG_CS_TIM_SHIFT) & EMIF_REG_CS_TIM_MASK)|\
        ((REG_SR_TIM << EMIF_REG_SR_TIM_SHIFT) & EMIF_REG_SR_TIM_MASK)|\
        ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\
-       ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\
        ((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)\
                        & EMIF_REG_LP_MODE_MASK) |\
        ((DPD_DISABLE << EMIF_REG_DPD_EN_SHIFT)\
@@ -878,8 +888,6 @@ struct dmm_lisa_map_regs {
                        & EMIF_REG_CS_TIM_SHDW_MASK) |\
        ((REG_SR_TIM << EMIF_REG_SR_TIM_SHDW_SHIFT)\
                        & EMIF_REG_SR_TIM_SHDW_MASK) |\
-       ((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\
-                       & EMIF_REG_PD_TIM_SHDW_MASK) |\
        ((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\
                        & EMIF_REG_PD_TIM_SHDW_MASK))
 
@@ -1112,6 +1120,7 @@ struct emif_regs {
        u32 freq;
        u32 sdram_config_init;
        u32 sdram_config;
+       u32 sdram_config2;
        u32 ref_ctrl;
        u32 sdram_tim1;
        u32 sdram_tim2;
@@ -1130,6 +1139,10 @@ struct emif_regs {
        u32 emif_rd_wr_lvl_rmp_ctl;
        u32 emif_rd_wr_lvl_ctl;
        u32 emif_rd_wr_exec_thresh;
+       u32 emif_prio_class_serv_map;
+       u32 emif_connect_id_serv_1_map;
+       u32 emif_connect_id_serv_2_map;
+       u32 emif_cos_config;
 };
 
 struct lpddr2_mr_regs {
@@ -1140,6 +1153,33 @@ struct lpddr2_mr_regs {
        s8 mr16;
 };
 
+struct read_write_regs {
+       u32 read_reg;
+       u32 write_reg;
+};
+
+static inline u32 get_emif_rev(u32 base)
+{
+       struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+       return (readl(&emif->emif_mod_id_rev) & EMIF_REG_MAJOR_REVISION_MASK)
+               >> EMIF_REG_MAJOR_REVISION_SHIFT;
+}
+
+/*
+ * Get SDRAM type connected to EMIF.
+ * Assuming similar SDRAM parts are connected to both EMIF's
+ * which is typically the case. So it is sufficient to get
+ * SDRAM type from EMIF1.
+ */
+static inline u32 emif_sdram_type(void)
+{
+       struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
+
+       return (readl(&emif->emif_sdram_config) &
+               EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
+}
+
 /* assert macros */
 #if defined(DEBUG)
 #define emif_assert(c) ({ if (!(c)) for (;;); })
@@ -1164,9 +1204,9 @@ void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs);
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 extern u32 *const T_num;
 extern u32 *const T_den;
-extern u32 *const emif_sizes;
 #endif
 
 void config_data_eye_leveling_samples(u32 emif_base);
 u32 emif_sdram_type(void);
+const struct read_write_regs *get_bug_regs(u32 *iterations);
 #endif