Merge branch 'master' of git://git.denx.de/u-boot-atmel

[karo-tx-uboot.git] / arch / microblaze / cpu / start.S

diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index 8564c4e30ab5e70c6d1008c1cfcd3c8f14dfca9a..84c29e54091e68819891f165a30d6c0eeac1c285 100644 (file)
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -5,23 +5,7 @@
  * Michal  SIMEK <monstr@monstr.eu>
  * Yasushi SHOJI <yashi@atmark-techno.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <asm-offsets.h>
@@ -38,7 +22,16 @@ _start:
         */
 
        mts     rmsr, r0        /* disable cache */
+
+       addi    r8, r0, __end
+       mts     rslr, r8
+#if defined(CONFIG_SPL_BUILD)
+       addi    r1, r0, CONFIG_SPL_STACK_ADDR
+       mts     rshr, r1
+       addi    r1, r1, -4      /* Decrement SP to top of memory */
+#else
        addi    r1, r0, CONFIG_SYS_INIT_SP_OFFSET
+       mts     rshr, r1
        addi    r1, r1, -4      /* Decrement SP to top of memory */
 
        /* Find-out if u-boot is running on BIG/LITTLE endian platform
@@ -131,10 +124,17 @@ _start:
        sh      r7, r0, r8
        rsubi   r8, r10, 0x26
        sh      r6, r0, r8
+#endif /* BUILD_SPL */
+
+       /* Flush cache before enable cache */
+       addik   r5, r0, 0
+       addik   r6, r0, XILINX_DCACHE_BYTE_SIZE
+flush: bralid r15, flush_cache
+       nop
 
        /* enable instruction and data cache */
        mfs     r12, rmsr
-       ori     r12, r12, 0xa0
+       ori     r12, r12, 0x1a0
        mts     rmsr, r12
 
 clear_bss:
@@ -149,9 +149,14 @@ clear_bss:
        cmp     r6, r5, r4 /* check if we have reach the end */
        bnei    r6, 2b
 3:     /* jumping to board_init */
+#ifndef CONFIG_SPL_BUILD
        brai    board_init_f
+#else
+       brai    board_init_r
+#endif
 1:     bri     1b
 
+#ifndef CONFIG_SPL_BUILD
 /*
  * Read 16bit little endian
  */
@@ -184,3 +189,4 @@ out16:      bslli   r3, r6, 8
        rtsd    r15, 8
        or      r0, r0, r0
        .end    out16
+#endif