MIPS: mips32/cache.S: store cache line size in t8 register

[karo-tx-uboot.git] / arch / mips / cpu / mips32 / cache.S

diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
index 40bb46e5b68bf25d9d3ad860ba9714d22f64dc14..d3f156e4822a908738e9e96cdc793a937506b249 100644 (file)
--- a/arch/mips/cpu/mips32/cache.S
+++ b/arch/mips/cpu/mips32/cache.S
@@ -18,7 +18,7 @@
 #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
 #endif
 
-#define RA             t8
+#define RA             t9
 
 /*
  * 16kB is the maximum size of instruction and data caches on MIPS 4K,
@@ -128,7 +128,7 @@ NESTED(mips_cache_reset, 0, ra)
        move    RA, ra
        li      t2, CONFIG_SYS_ICACHE_SIZE
        li      t3, CONFIG_SYS_DCACHE_SIZE
-       li      t4, CONFIG_SYS_CACHELINE_SIZE
+       li      t8, CONFIG_SYS_CACHELINE_SIZE
 
        li      v0, MIPS_MAX_CACHE_SIZE
 
@@ -155,7 +155,7 @@ NESTED(mips_cache_reset, 0, ra)
         * Initialize the I-cache first,
         */
        move    a1, t2
-       move    a2, t4
+       move    a2, t8
        PTR_LA  t7, mips_init_icache
        jalr    t7
 
@@ -163,7 +163,7 @@ NESTED(mips_cache_reset, 0, ra)
         * then initialize D-cache.
         */
        move    a1, t3
-       move    a2, t4
+       move    a2, t8
        PTR_LA  t7, mips_init_dcache
        jalr    t7