powerpc/85xx: fix compatible property for the L2 cache node

[karo-tx-uboot.git] / arch / powerpc / cpu / mpc85xx / fdt.c

diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 45403641cfa03eca0a805e9482eda5137a1d9df2..97d3928e1d5124f908c543a9bfe90ad0e9c8f063 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2010 Freescale Semiconductor, Inc.
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -38,6 +38,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 extern void ft_qe_setup(void *blob);
 extern void ft_fixup_num_cores(void *blob);
+extern void ft_srio_setup(void *blob);
 
 #ifdef CONFIG_MP
 #include "mp.h"
@@ -48,6 +49,7 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
        ulong spin_tbl_addr = get_spin_phys_addr();
        u32 bootpg = determine_mp_bootpg();
        u32 id = get_my_id();
+       const char *enable_method;
 
        off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
        while (off != -FDT_ERR_NOTFOUND) {
@@ -63,10 +65,25 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
                                fdt_setprop_string(blob, off, "status",
                                                                "disabled");
                        }
+
+                       if (hold_cores_in_reset(0)) {
+#ifdef CONFIG_FSL_CORENET
+                               /* Cores held in reset, use BRR to release */
+                               enable_method = "fsl,brr-holdoff";
+#else
+                               /* Cores held in reset, use EEBPCR to release */
+                               enable_method = "fsl,eebpcr-holdoff";
+#endif
+                       } else {
+                               /* Cores out of reset and in a spin-loop */
+                               enable_method = "spin-table";
+
+                               fdt_setprop(blob, off, "cpu-release-addr",
+                                               &val, sizeof(val));
+                       }
+
                        fdt_setprop_string(blob, off, "enable-method",
-                                                       "spin-table");
-                       fdt_setprop(blob, off, "cpu-release-addr",
-                                       &val, sizeof(val));
+                                                       enable_method);
                } else {
                        printf ("cpu NULL\n");
                }
@@ -148,7 +165,6 @@ static inline void ft_fixup_l2cache(void *blob)
        int len, off;
        u32 *ph;
        struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
-       char compat_buf[38];
 
        const u32 line_size = 32;
        const u32 num_ways = 8;
@@ -175,22 +191,32 @@ static inline void ft_fixup_l2cache(void *blob)
        }
 
        if (cpu) {
-               if (isdigit(cpu->name[0]))
-                       len = sprintf(compat_buf,
-                               "fsl,mpc%s-l2-cache-controller", cpu->name);
-               else
-                       len = sprintf(compat_buf,
-                               "fsl,%c%s-l2-cache-controller",
-                               tolower(cpu->name[0]), cpu->name + 1);
+               char buf[40];
+
+               if (isdigit(cpu->name[0])) {
+                       /* MPCxxxx, where xxxx == 4-digit number */
+                       len = sprintf(buf, "fsl,mpc%s-l2-cache-controller",
+                               cpu->name) + 1;
+               } else {
+                       /* Pxxxx or Txxxx, where xxxx == 4-digit number */
+                       len = sprintf(buf, "fsl,%c%s-l2-cache-controller",
+                               tolower(cpu->name[0]), cpu->name + 1) + 1;
+               }
 
-               sprintf(&compat_buf[len + 1], "cache");
+               /*
+                * append "cache" after the NULL character that the previous
+                * sprintf wrote.  This is how a device tree stores multiple
+                * strings in a property.
+                */
+               len += sprintf(buf + len, "cache") + 1;
+
+               fdt_setprop(blob, off, "compatible", buf, len);
        }
        fdt_setprop(blob, off, "cache-unified", NULL, 0);
        fdt_setprop_cell(blob, off, "cache-block-size", line_size);
        fdt_setprop_cell(blob, off, "cache-size", size);
        fdt_setprop_cell(blob, off, "cache-sets", num_sets);
        fdt_setprop_cell(blob, off, "cache-level", 2);
-       fdt_setprop(blob, off, "compatible", compat_buf, sizeof(compat_buf));
 
        /* we dont bother w/L3 since no platform of this type has one */
 }
@@ -321,6 +347,9 @@ void fdt_add_enet_stashing(void *fdt)
        do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1);
 
        do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1);
+       do_fixup_by_compat(fdt, "fsl,etsec2", "bd-stash", NULL, 0, 1);
+       do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-len", 96, 1);
+       do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-idx", 0, 1);
 }
 
 #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME)
@@ -453,6 +482,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
        fdt_portal(blob, "fsl,bman-portal", "bman-portals",
                        (u64)CONFIG_SYS_BMAN_MEM_PHYS,
                        CONFIG_SYS_BMAN_MEM_SIZE);
+       fdt_fixup_bportals(blob);
 #endif
 
 #if defined(CONFIG_SYS_QMAN_MEM_PHYS)
@@ -462,4 +492,17 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 
        fdt_fixup_qportals(blob);
 #endif
+
+#ifdef CONFIG_SYS_SRIO
+       ft_srio_setup(blob);
+#endif
+
+       /*
+        * system-clock = CCB clock/2
+        * Here gd->bus_clk = CCB clock
+        * We are using the system clock as 1588 Timer reference
+        * clock source select
+        */
+       do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer",
+                       "timer-frequency", gd->bus_clk/2, 1);
 }