/*
- * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2007-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
#include <tsec.h>
#include <netdev.h>
-#include "../common/pixis.h"
#include "../common/sgmii_riser.h"
long int fixed_sdram(void);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
SET_STD_PCIE_INFO(pci_info[num], 3);
pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
- printf (" PCIE3 connected to ULI as %s (base addr %lx)\n",
- pcie_ep ? "Endpoint" : "Root Complex",
- pci_info[num].regs);
+ printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie3_hose, first_free_busno);
/*
in_be32(p);
}
} else {
- printf (" PCIE3: disabled\n");
+ printf("PCIE3: disabled\n");
}
puts("\n");
#else
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
SET_STD_PCIE_INFO(pci_info[num], 2);
pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
- printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
- pcie_ep ? "Endpoint" : "Root Complex",
- pci_info[num].regs);
+ printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie2_hose, first_free_busno);
} else {
- printf (" PCIE2: disabled\n");
+ printf("PCIE2: disabled\n");
}
puts("\n");
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
SET_STD_PCIE_INFO(pci_info[num], 1);
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
- printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
+ printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);
} else {
- printf (" PCIE1: disabled\n");
+ printf("PCIE1: disabled\n");
}
puts("\n");
return 0;
}
-#ifdef CONFIG_GET_CLK_FROM_ICS307
-/* decode S[0-2] to Output Divider (OD) */
-static unsigned char ics307_S_to_OD[] = {
- 10, 2, 8, 4, 5, 7, 3, 6
-};
-
-/* Calculate frequency being generated by ICS307-02 clock chip based upon
- * the control bytes being programmed into it. */
-/* XXX: This function should probably go into a common library */
-static unsigned long
-ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
-{
- const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
- unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
- unsigned long RDW = cw2 & 0x7F;
- unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
- unsigned long freq;
-
- /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
-
- /* cw0: C1 C0 TTL F1 F0 S2 S1 S0
- * cw1: V8 V7 V6 V5 V4 V3 V2 V1
- * cw2: V0 R6 R5 R4 R3 R2 R1 R0
- *
- * R6:R0 = Reference Divider Word (RDW)
- * V8:V0 = VCO Divider Word (VDW)
- * S2:S0 = Output Divider Select (OD)
- * F1:F0 = Function of CLK2 Output
- * TTL = duty cycle
- * C1:C0 = internal load capacitance for cyrstal
- */
-
- /* Adding 1 to get a "nicely" rounded number, but this needs
- * more tweaking to get a "properly" rounded number. */
-
- freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
-
- debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2,
- freq);
- return freq;
-}
-
-unsigned long get_board_sys_clk(ulong dummy)
-{
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- return ics307_clk_freq (
- in_8(pixis_base + PIXIS_VSYSCLK0),
- in_8(pixis_base + PIXIS_VSYSCLK1),
- in_8(pixis_base + PIXIS_VSYSCLK2)
- );
-}
-
-unsigned long get_board_ddr_clk(ulong dummy)
-{
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- return ics307_clk_freq (
- in_8(pixis_base + PIXIS_VDDRCLK0),
- in_8(pixis_base + PIXIS_VDDRCLK1),
- in_8(pixis_base + PIXIS_VDDRCLK2)
- );
-}
-#else
-unsigned long get_board_sys_clk(ulong dummy)
-{
- u8 i;
- ulong val = 0;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- i = in_8(pixis_base + PIXIS_SPD);
- i &= 0x07;
-
- switch (i) {
- case 0:
- val = 33333333;
- break;
- case 1:
- val = 40000000;
- break;
- case 2:
- val = 50000000;
- break;
- case 3:
- val = 66666666;
- break;
- case 4:
- val = 83333333;
- break;
- case 5:
- val = 100000000;
- break;
- case 6:
- val = 133333333;
- break;
- case 7:
- val = 166666666;
- break;
- }
-
- return val;
-}
-
-unsigned long get_board_ddr_clk(ulong dummy)
-{
- u8 i;
- ulong val = 0;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- i = in_8(pixis_base + PIXIS_SPD);
- i &= 0x38;
- i >>= 3;
-
- switch (i) {
- case 0:
- val = 33333333;
- break;
- case 1:
- val = 40000000;
- break;
- case 2:
- val = 50000000;
- break;
- case 3:
- val = 66666666;
- break;
- case 4:
- val = 83333333;
- break;
- case 5:
- val = 100000000;
- break;
- case 6:
- val = 133333333;
- break;
- case 7:
- val = 166666666;
- break;
- }
- return val;
-}
-#endif
-
#ifdef CONFIG_TSEC_ENET
int board_eth_init(bd_t *bis)
{
fdt_fixup_memory(blob, (u64)base, (u64)size);
-#ifdef CONFIG_PCIE3
- ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
-#endif
-#ifdef CONFIG_PCIE2
- ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
-#endif
-#ifdef CONFIG_PCIE1
- ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
-#endif
+ FT_FSL_PCI_SETUP;
+
#ifdef CONFIG_FSL_SGMII_RISER
fsl_sgmii_riser_fdt_fixup(blob);
#endif
projects / karo-tx-uboot.git / blobdiff