Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

[karo-tx-uboot.git] / board / freescale / mx6sabresd / mx6sabresd.c

diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 1340f29d76272dbc8fb5bc4b5f129d7f5c658d51..81dcd6e5ddb879ae3aa4ed9e8a0e800b63929459 100644 (file)
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -12,6 +12,7 @@
 #include <asm/arch/mx6-pins.h>
 #include <asm/errno.h>
 #include <asm/gpio.h>
+#include <asm/imx-common/mxc_i2c.h>
 #include <asm/imx-common/iomux-v3.h>
 #include <asm/imx-common/boot_mode.h>
 #include <asm/imx-common/video.h>
@@ -23,6 +24,9 @@
 #include <asm/arch/crm_regs.h>
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
 DECLARE_GLOBAL_DATA_PTR;
 
 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                  \
@@ -39,6 +43,14 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
                      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
 
+#define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
+       PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define I2C_PMIC       1
+
+#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
+
 int dram_init(void)
 {
        gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -129,6 +141,19 @@ iomux_v3_cfg_t const ecspi1_pads[] = {
        MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
+static struct i2c_pads_info i2c_pad_info1 = {
+       .scl = {
+               .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
+               .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
+               .gp = IMX_GPIO_NR(4, 12)
+       },
+       .sda = {
+               .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
+               .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
+               .gp = IMX_GPIO_NR(4, 13)
+       }
+};
+
 static void setup_spi(void)
 {
        imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
@@ -264,14 +289,6 @@ int board_phy_config(struct phy_device *phydev)
 }
 
 #if defined(CONFIG_VIDEO_IPUV3)
-
-static int detect_hdmi(struct display_info_t const *dev)
-{
-       struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
-       return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
-}
-
-
 static void disable_lvds(struct display_info_t const *dev)
 {
        struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
@@ -434,10 +451,75 @@ int board_init(void)
 #ifdef CONFIG_MXC_SPI
        setup_spi();
 #endif
+       setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 
        return 0;
 }
 
+static int pfuze_init(void)
+{
+       struct pmic *p;
+       int ret;
+       unsigned int reg;
+
+       ret = power_pfuze100_init(I2C_PMIC);
+       if (ret)
+               return ret;
+
+       p = pmic_get("PFUZE100");
+       ret = pmic_probe(p);
+       if (ret)
+               return ret;
+
+       pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+       printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
+
+       /* Increase VGEN3 from 2.5 to 2.8V */
+       pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
+       reg &= ~0xf;
+       reg |= 0xa;
+       pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
+
+       /* Increase VGEN5 from 2.8 to 3V */
+       pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
+       reg &= ~0xf;
+       reg |= 0xc;
+       pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
+
+       /* Set SW1AB stanby volage to 0.975V */
+       pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
+       reg &= ~0x3f;
+       reg |= 0x1b;
+       pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
+
+       /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+       pmic_reg_read(p, PUZE_100_SW1ABCONF, &reg);
+       reg &= ~0xc0;
+       reg |= 0x40;
+       pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
+
+       /* Set SW1C standby voltage to 0.975V */
+       pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
+       reg &= ~0x3f;
+       reg |= 0x1b;
+       pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
+
+       /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
+       pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
+       reg &= ~0xc0;
+       reg |= 0x40;
+       pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
+
+       return 0;
+}
+
+#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+       return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
+}
+#endif
+
 #ifdef CONFIG_CMD_BMODE
 static const struct boot_mode board_boot_modes[] = {
        /* 4 bit bus width */
@@ -454,6 +536,7 @@ int board_late_init(void)
 #ifdef CONFIG_CMD_BMODE
        add_board_boot_modes(board_boot_modes);
 #endif
+       pfuze_init();
 
        return 0;
 }