rename CFG_ macros to CONFIG_SYS

[karo-tx-uboot.git] / board / idmr / idmr.c

diff --git a/board/idmr/idmr.c b/board/idmr/idmr.c
index 081c37533591c0c09d5c64c352c3b631dc5064e4..3771c191e10be2aa486736e2a0da77528af636bb 100644 (file)
--- a/board/idmr/idmr.c
+++ b/board/idmr/idmr.c
@@ -29,13 +29,13 @@ int checkboard (void) {
        return 0;
 };
 
-long int initdram (int board_type) {
+phys_size_t initdram (int board_type) {
        int i;
 
        /*
         * After reset, CS0 is configured to cover entire address space. We
         * need to configure it to its proper values, so that writes to
-        * CFG_SDRAM_BASE and vicinity during SDRAM controller setup below do
+        * CONFIG_SYS_SDRAM_BASE and vicinity during SDRAM controller setup below do
         * now fall under CS0 (see 16.3.1 of the MCF5271 Reference Manual).
         */
 
@@ -99,7 +99,7 @@ long int initdram (int board_type) {
         * PS: 16 bit
         */
        mbar_writeLong(MCF_SDRAMC_DACR0,
-                       MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18) |
+                       MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18) |
                        MCF_SDRAMC_DACRn_BA(0x00) |
                        MCF_SDRAMC_DACRn_CASL(0x03) |
                        MCF_SDRAMC_DACRn_CBM(0x03) |
@@ -117,7 +117,7 @@ long int initdram (int board_type) {
                        MCF_SDRAMC_DACRn_IP);
 
        /* Write to this block to initiate precharge */
-       *(volatile u16 *)(CFG_SDRAM_BASE) = 0xa5a5;
+       *(volatile u16 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5;
 
        /*
         * Wait at least 20ns to allow banks to precharge (t_RP = 20ns). We
@@ -153,9 +153,9 @@ long int initdram (int board_type) {
         * Burst Type = Sequential
         * Burst Length = 1
         */
-       *(volatile u32 *)(CFG_SDRAM_BASE + 0x1800) = 0xa5a5a5a5;
+       *(volatile u32 *)(CONFIG_SYS_SDRAM_BASE + 0x1800) = 0xa5a5a5a5;
 
-       return CFG_SDRAM_SIZE * 1024 * 1024;
+       return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 };