karo: tx6: disable gpmi clk before changing podf and clk_sel

[karo-tx-uboot.git] / board / karo / tx6 / tx6ul_ll_init.S

diff --git a/board/karo/tx6/tx6ul_ll_init.S b/board/karo/tx6/tx6ul_ll_init.S
index 1a0e9b82b0775937aa8d8087bfc48ae5e110165a..bdd2214c9a4dceee5c515d85e5fed02dab5fec92 100644 (file)
--- a/board/karo/tx6/tx6ul_ll_init.S
+++ b/board/karo/tx6/tx6ul_ll_init.S
@@ -22,6 +22,8 @@
 #define SDRAM_SIZE             PHYS_SDRAM_1_SIZE
 #endif
 
+#define CCGR(m)                        (3 << ((m) * 2))
+
 #define CPU_2_BE_32(l)                 \
        ((((l) << 24) & 0xFF000000) |   \
        (((l) << 8) & 0x00FF0000) |     \
@@ -510,7 +512,7 @@ ivt_end:
 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET       0x020e0288
 
 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK     0x020e0368
-#define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK     0x020e037c
+#define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK     0x020e0388
 #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B                0x020e0404
 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B                0x020e0408
 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00      0x020e040c
@@ -548,9 +550,9 @@ dcd_hdr:
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER1, 0x0000f0b9)
        /* ENET_REF_CLK */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK, 0x00000014)
-       MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK, 0x000010b0)
+       MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK, 0x000000b1)
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK, 0x00000014)
-       MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK, 0x000010b0)
+       MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK, 0x000000b1)
        MXC_DCD_ITEM(IOMUXC_ENET1_REF_CLK1_SELECT_INPUT, 2)
        MXC_DCD_ITEM(IOMUXC_ENET2_REF_CLK2_SELECT_INPUT, 2)
        /* ETN PHY nRST */
@@ -559,11 +561,22 @@ dcd_hdr:
        /* ETN PHY Power */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER5, 0x00000015)
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER5, 0x000010b0)
-       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x006336c1) /* default: 0x000336c1 */
+#ifndef CONFIG_TX6_EMMC
+       /* switch NFC clock to 99MHz */
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CLR)
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(14))
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(7))
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x0061b6c1) /* default: 0x000336c1 */
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET)
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(14))
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(7))
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+#endif
        MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CSCDR2, 0x00012090) /* default: 0x0002a150 */
 
        MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002005) /* ENET PLL */
-#define CCGR(m)                (3 << ((m) * 2))
+
        /* enable all relevant clocks... */
        MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET)
        /* enable UART clock depending on selected console port */
@@ -592,15 +605,16 @@ dcd_hdr:
 #else
        MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, CCGR(1)) /* default: 0x00fc3003 USDHC1 */
 #endif
-       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+       MXC_DCD_ITEM(IOMUXC_GPR1, 0x00020000) /* default: 0x0f400005 ENET1_TX_CLK output */
 
-       MXC_DCD_ITEM(0x020c80a0, 0x80082029) /* set video PLL to 984MHz */
-       MXC_DCD_ITEM(0x020c80b0, 0x00065b9a)
-       MXC_DCD_ITEM(0x020c80c0, 0x000f4240)
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+       MXC_DCD_ITEM(0x020c80b0, 0)
+       MXC_DCD_ITEM(0x020c80c0, 1)
+       MXC_DCD_ITEM(0x020c80a0, 0x0010201b) /* set video PLL to 648MHz */
 
        /* IOMUX: */
        MXC_DCD_ITEM(IOMUXC_GPR0, 0x00000000)
-       MXC_DCD_ITEM(IOMUXC_GPR1, 0x0f460005) /* default: 0x0f400005 ENET1_TX_CLK output */
+       MXC_DCD_ITEM(IOMUXC_GPR1, 0x0f460005) /* default: 0x0f400005 ENET[12]_TX_CLK output */
        MXC_DCD_ITEM(IOMUXC_GPR2, 0x00000000)
        MXC_DCD_ITEM(IOMUXC_GPR3, 0x00000fff)
        MXC_DCD_ITEM(IOMUXC_GPR4, 0x00000100)