imported Freescale specific U-Boot additions for i.MX28,... release L2.6.31_10.08.01

[karo-tx-uboot.git] / board / mpl / mip405 / mip405.h

diff --git a/board/mpl/mip405/mip405.h b/board/mpl/mip405/mip405.h
index b1d91deece4792c1145ac7a7247fac9ce0f56372..fd7e78a45d4d35f9ff77d998420f51e0b40c8ee2 100755 (executable)
--- a/board/mpl/mip405/mip405.h
+++ b/board/mpl/mip405/mip405.h
@@ -35,7 +35,7 @@ void user_led0(unsigned char on);
 #endif
 /* timings */
 /* PLD (CS7) */
-#define PLD_BME        0       /* Burst disable */
+#define PLD_BME        0       /* Burst disable */
 #define PLD_TWE        5       /* 5 * 30ns 120ns Waitstates (access=TWT+1+TH) */
 #define PLD_CSN        1       /* Chipselect is driven inactive for 1 Cycle BTW transfers */
 #define PLD_OEN        1       /* Cycles from CS low to OE low   */
@@ -46,7 +46,7 @@ void user_led0(unsigned char on);
 #define PLD_SOR        1       /* Sample on Ready disabled */
 #define PLD_BEM        0       /* Byte Write only active on Write cycles */
 #define PLD_PEN        0       /* Parity disable */
-#define PLD_AP         ((PLD_BME << 31) + (PLD_TWE << 23) + (PLD_CSN << 18) + (PLD_OEN << 16) + (PLD_WBN << 14) + \
+#define PLD_AP ((PLD_BME << 31) + (PLD_TWE << 23) + (PLD_CSN << 18) + (PLD_OEN << 16) + (PLD_WBN << 14) + \
                                        (PLD_WBF << 12) + (PLD_TH << 9) + (PLD_RE << 8) + (PLD_SOR << 7) + (PLD_BEM << 6) + (PLD_PEN << 5))
 
 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
@@ -62,7 +62,7 @@ void user_led0(unsigned char on);
 
 #define PER_BOARD_ADDR (PER_UART1_ADDR+(1024*1024))
 /* Dummy CS to get the board revision */
-#define BOARD_BME      0       /* Burst disable */
+#define BOARD_BME      0       /* Burst disable */
 #define BOARD_TWE      255     /* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */
 #define BOARD_CSN      1       /* Chipselect is driven inactive for 1 Cycle BTW transfers */
 #define BOARD_OEN      1       /* Cycles from CS low to OE low   */
@@ -73,7 +73,7 @@ void user_led0(unsigned char on);
 #define BOARD_SOR      1       /* Sample on Ready disabled */
 #define BOARD_BEM      0       /* Byte Write only active on Write cycles */
 #define BOARD_PEN      0       /* Parity disable */
-#define BOARD_AP       ((BOARD_BME << 31) + (BOARD_TWE << 23) + (BOARD_CSN << 18) + (BOARD_OEN << 16) + (BOARD_WBN << 14) + \
+#define BOARD_AP       ((BOARD_BME << 31) + (BOARD_TWE << 23) + (BOARD_CSN << 18) + (BOARD_OEN << 16) + (BOARD_WBN << 14) + \
                                        (BOARD_WBF << 12) + (BOARD_TH << 9) + (BOARD_RE << 8) + (BOARD_SOR << 7) + (BOARD_BEM << 6) + (BOARD_PEN << 5))
 
 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
@@ -86,7 +86,7 @@ void user_led0(unsigned char on);
 
 
 /* UART0 CS2 */
-#define UART0_BME      0       /* Burst disable */
+#define UART0_BME      0       /* Burst disable */
 #define UART0_TWE      7       /* 7 * 30ns 210ns Waitstates (access=TWT+1+TH) */
 #define UART0_CSN      1       /* Chipselect is driven inactive for 1 Cycle BTW transfers */
 #define UART0_OEN      1       /* Cycles from CS low to OE low   */
@@ -97,7 +97,7 @@ void user_led0(unsigned char on);
 #define UART0_SOR      1       /* Sample on Ready disabled */
 #define UART0_BEM      0       /* Byte Write only active on Write cycles */
 #define UART0_PEN      0       /* Parity disable */
-#define UART0_AP       ((UART0_BME << 31) + (UART0_TWE << 23) + (UART0_CSN << 18) + (UART0_OEN << 16) + (UART0_WBN << 14) + \
+#define UART0_AP       ((UART0_BME << 31) + (UART0_TWE << 23) + (UART0_CSN << 18) + (UART0_OEN << 16) + (UART0_WBN << 14) + \
                                        (UART0_WBF << 12) + (UART0_TH << 9) + (UART0_RE << 8) + (UART0_SOR << 7) + (UART0_BEM << 6) + (UART0_PEN << 5))
 
 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
@@ -115,10 +115,10 @@ void user_led0(unsigned char on);
 
 /* Flash CS0 or CS 1 */
 /* 0x7F8FFE80 slowest timing at all... */
-#define FLASH_BME_B    1       /* Burst enable */
+#define FLASH_BME_B    1       /* Burst enable */
 #define FLASH_FWT_B    0x6     /* 6 * 30ns 210ns First Wait Access */
 #define FLASH_BWT_B    0x6     /* 6 * 30ns 210ns Burst Wait Access */
-#define FLASH_BME      0       /* Burst disable */
+#define FLASH_BME      0       /* Burst disable */
 #define FLASH_TWE      0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
 #define FLASH_CSN      0       /* Chipselect is driven inactive for 1 Cycle BTW transfers */
 #define FLASH_OEN      1       /* Cycles from CS low to OE low   */
@@ -130,10 +130,10 @@ void user_led0(unsigned char on);
 #define FLASH_BEM      0       /* Byte Write only active on Write cycles */
 #define FLASH_PEN      0       /* Parity disable */
 /* Access Parameter Register for non Boot */
-#define FLASH_AP       ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
+#define FLASH_AP       ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
                                        (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
 /* Access Parameter Register for Boot */
-#define FLASH_AP_B     ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
+#define FLASH_AP_B     ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
                                        (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
 
 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
@@ -149,10 +149,10 @@ void user_led0(unsigned char on);
 
 /* MPS CS1 or CS0 */
 /* Boot CS: */
-#define MPS_BME_B      1       /* Burst enable */
+#define MPS_BME_B      1       /* Burst enable */
 #define MPS_FWT_B      0x6/* 6 * 30ns 210ns First Wait Access */
 #define MPS_BWT_B      0x6     /* 6 * 30ns 210ns Burst Wait Access */
-#define MPS_BME                0       /* Burst disable */
+#define MPS_BME                0       /* Burst disable */
 #define MPS_TWE                0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
 #define MPS_CSN                0       /* Chipselect is driven inactive for 1 Cycle BTW transfers */
 #define MPS_OEN                1       /* Cycles from CS low to OE low   */
@@ -164,10 +164,10 @@ void user_led0(unsigned char on);
 #define MPS_BEM                0       /* Byte Write only active on Write cycles */
 #define MPS_PEN                0       /* Parity disable */
 /* Access Parameter Register for non Boot */
-#define MPS_AP                 ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
+#define MPS_AP         ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
                                        (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
 /* Access Parameter Register for Boot */
-#define MPS_AP_B               ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
+#define MPS_AP_B               ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
                                        (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
 
 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */