GCC-4.x fixes: clean up global data pointer initialization for all boards.

[karo-tx-uboot.git] / board / mx1ads / mx1ads.c

diff --git a/board/mx1ads/mx1ads.c b/board/mx1ads/mx1ads.c
index 5c33ba3c0ea8354122425cc4c54bde63dbd3cbe6..913f95c5e89180e97f4c2f23512335a200aa4a6c 100644 (file)
--- a/board/mx1ads/mx1ads.c
+++ b/board/mx1ads/mx1ads.c
@@ -27,7 +27,7 @@
 /*#include <mc9328.h>*/
 #include <asm/arch/imx-regs.h>
 
-/* ------------------------------------------------------------------------- */
+DECLARE_GLOBAL_DATA_PTR;
 
 #define FCLK_SPEED 1
 
@@ -55,10 +55,11 @@
 
 #if 0
 
-static inline void delay (unsigned long loops) {
+static inline void delay (unsigned long loops)
+{
        __asm__ volatile ("1:\n"
-         "subs %0, %1, #1\n"
-         "bne 1b":"=r" (loops):"0" (loops));
+                         "subs %0, %1, #1\n"
+                         "bne 1b":"=r" (loops):"0" (loops));
 }
 
 #endif
@@ -67,62 +68,58 @@ static inline void delay (unsigned long loops) {
  * Miscellaneous platform dependent initialisations
  */
 
-void SetAsynchMode(void) {
-       __asm__ (
-               "mrc p15,0,r0,c1,c0,0 \n"
-               "mov r2, #0xC0000000 \n"
-               "orr r0,r2,r0 \n"
-               "mcr p15,0,r0,c1,c0,0 \n"
-       );
+void SetAsynchMode (void)
+{
+       __asm__ ("mrc p15,0,r0,c1,c0,0 \n"
+                "mov r2, #0xC0000000 \n"
+                "orr r0,r2,r0 \n" "mcr p15,0,r0,c1,c0,0 \n");
 }
 
 static u32 mc9328sid;
 
-int board_init (void) {
+int board_init (void)
+{
+       volatile unsigned int tmp;
 
-       DECLARE_GLOBAL_DATA_PTR;
+       mc9328sid = SIDR;
 
-       volatile unsigned int  tmp;
+       GPCR = 0x000003AB;      /* I/O pad driving strength     */
 
-       mc9328sid       = SIDR;
-
-       GPCR            = 0x000003AB;           /* I/O pad driving strength     */
-
-/*     MX1_CS1U        = 0x00000A00;   */      /* SRAM initialization          */
+       /*      MX1_CS1U        = 0x00000A00;   *//* SRAM initialization          */
 /*     MX1_CS1L        = 0x11110601;   */
 
-       MPCTL0          = 0x04632410;   /* setting for 150 MHz MCU PLL CLK      */
+       MPCTL0 = 0x04632410;    /* setting for 150 MHz MCU PLL CLK      */
 
 /* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and
  * BCLK divider to 2 (i.e. BCLK to 48 MHz)
  */
-       CSCR    = 0xAF000403;
+       CSCR = 0xAF000403;
 
-       CSCR    |= 0x00200000;          /* Trigger the restart bit(bit 21)      */
-       CSCR    &= 0xFFFF7FFF;          /* Program PRESC bit(bit 15) to 0 to divide-by-1 */
+       CSCR |= 0x00200000;     /* Trigger the restart bit(bit 21)      */
+       CSCR &= 0xFFFF7FFF;     /* Program PRESC bit(bit 15) to 0 to divide-by-1 */
 
 /* setup cs4 for cs8900 ethernet */
 
-       CS4U    = 0x00000F00;   /* Initialize CS4 for CS8900 ethernet   */
-       CS4L    = 0x00001501;
+       CS4U = 0x00000F00;      /* Initialize CS4 for CS8900 ethernet   */
+       CS4L = 0x00001501;
 
-       GIUS(0) &= 0xFF3FFFFF;
-       GPR(0)  &= 0xFF3FFFFF;
+       GIUS (0) &= 0xFF3FFFFF;
+       GPR (0) &= 0xFF3FFFFF;
 
-       tmp = *(unsigned int *)(0x1500000C);
-       tmp = *(unsigned int *)(0x1500000C);
+       tmp = *(unsigned int *) (0x1500000C);
+       tmp = *(unsigned int *) (0x1500000C);
 
-       SetAsynchMode();
+       SetAsynchMode ();
 
        gd->bd->bi_arch_number = MACH_TYPE_MX1ADS;
 
-       gd->bd->bi_boot_params = 0x08000100;    /* adress of boot parameters    */
+       gd->bd->bi_boot_params = 0x08000100;    /* adress of boot parameters    */
 
-       icache_enable();
-       dcache_enable();
+       icache_enable ();
+       dcache_enable ();
 
 /* set PERCLKs                         */
-       PCDR = 0x00000055;      /* set PERCLKS                          */
+       PCDR = 0x00000055;      /* set PERCLKS                          */
 
 /* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes
  * PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place
@@ -135,34 +132,38 @@ int board_init (void) {
        return 0;
 }
 
-int board_late_init(void) {
-
-       setenv("stdout", "serial");
-       setenv("stderr", "serial");
-
-       switch  (mc9328sid) {
-               case 0x0005901d :
-                       printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n",mc9328sid);
-                       break;
-               case 0x04d4c01d :
-                       printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n",mc9328sid);
-                       break;
-               case 0x00d4c01d :
-                       printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n",mc9328sid);
-                       break;
-
-               default :
-                       printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",mc9328sid);
-                       break;
+int board_late_init (void)
+{
+
+       setenv ("stdout", "serial");
+       setenv ("stderr", "serial");
+
+       switch (mc9328sid) {
+       case 0x0005901d:
+               printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n",
+                       mc9328sid);
+               break;
+       case 0x04d4c01d:
+               printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n",
+                       mc9328sid);
+               break;
+       case 0x00d4c01d:
+               printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n",
+                       mc9328sid);
+               break;
+
+       default:
+               printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",
+                       mc9328sid);
+               break;
        }
        return 0;
 }
 
-int dram_init (void) {
-       DECLARE_GLOBAL_DATA_PTR;
-
+int dram_init (void)
+{
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-       gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+       gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 
        return 0;
 }