imported Freescale specific U-Boot additions for i.MX28,... release L2.6.31_10.08.01

[karo-tx-uboot.git] / board / netta / dsp.c

diff --git a/board/netta/dsp.c b/board/netta/dsp.c
index 66e0b85e6c6b54e548387a6052a8fb533550a70a..cd576476ec8dce4aaaf2dc16ecd2a6ecef57e2ac 100755 (executable)
--- a/board/netta/dsp.c
+++ b/board/netta/dsp.c
@@ -95,7 +95,7 @@ static volatile u32 *ti6711_delay = &dummy_delay;
 
 static inline void dsp_go_slow(void)
 {
-       volatile memctl8xx_t *memctl = &((immap_t *)CFG_IMMR)->im_memctl;
+       volatile memctl8xx_t *memctl = &((immap_t *)CONFIG_SYS_IMMR)->im_memctl;
 #if defined(CONFIG_NETTA_6412)
        memctl->memc_or6 |= OR_SCY_15_CLK | OR_TRLX;
 #else
@@ -108,7 +108,7 @@ static inline void dsp_go_slow(void)
 
 static inline void dsp_go_fast(void)
 {
-       volatile memctl8xx_t *memctl = &((immap_t *)CFG_IMMR)->im_memctl;
+       volatile memctl8xx_t *memctl = &((immap_t *)CONFIG_SYS_IMMR)->im_memctl;
 #if defined(CONFIG_NETTA_6412)
        memctl->memc_or6 = (memctl->memc_or6 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_0_CLK;
 #else
@@ -148,14 +148,14 @@ static inline void dsp_write_hpic(u16 val)
 static inline void dsp_reset(void)
 {
 #if defined(CONFIG_NETTA_6412)
-       ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 15));
+       ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 15));
        udelay(500);
-       ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat |=  (1 << (15 - 15));
+       ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat |=  (1 << (15 - 15));
        udelay(500);
 #else
-       ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 7));
+       ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 7));
        udelay(250);
-       ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat |=  (1 << (15 - 7));
+       ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat |=  (1 << (15 - 7));
        udelay(250);
 #endif
 }
@@ -1031,7 +1031,7 @@ const struct host_init hi_default = {
 
        .clk_divider    = {
                [0]     = 47,           /* must be 2048Hz */
-               [1]     = 47,
+               [1]     = 47,
        },
 
        .initmode       = 1,