#define MSTPSR7 0xE61501C4
#define SMSTPCR7 0xE615014C
-#define SCIF0_MSTP719 (1 << 19)
+#define SCIF2_MSTP719 (1 << 19)
#define MSTPSR8 0xE61509A0
#define SMSTPCR8 0xE6150990
#define ETHER_MSTP813 (1 << 13)
+#define MSTPSR3 0xE6150048
+#define SMSTPCR3 0xE615013C
+#define IIC1_MSTP323 (1 << 23)
+
#define mstp_setbits(type, addr, saddr, set) \
out_##type((saddr), in_##type(addr) | (set))
#define mstp_clrbits(type, addr, saddr, clear) \
/* TMU */
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
- /* SCIF0 */
- mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP719);
+ /* SCIF2 */
+ mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719);
/* ETHER */
mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
+ /* IIC1 / sh-i2c ch1 */
+ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323);
+
return 0;
}
int dram_init(void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
gd->bd->bi_dram[0].size = ALT_SDRAM_SIZE;
}
-int board_late_init(void)
-{
- return 0;
-}
-
void reset_cpu(ulong addr)
{
u8 val;
- i2c_set_bus_num(1); /* PowerIC connected to ch3 */
- i2c_init(400000, 0);
+ i2c_set_bus_num(1); /* PowerIC connected to ch1 */
i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
val |= 0x02;
i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);