Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'

[karo-tx-uboot.git] / board / samsung / origen / origen_setup.h

diff --git a/board/samsung/origen/origen_setup.h b/board/samsung/origen/origen_setup.h
index 63d85d8a8c1e65d45c701fd502b48431ac3d06e9..926a4ccc2921151a09b5b9530fefece99dc27803 100644 (file)
--- a/board/samsung/origen/origen_setup.h
+++ b/board/samsung/origen/origen_setup.h
@@ -53,9 +53,22 @@
 #define CLK_DIV_FSYS2_OFFSET   0xC548
 #define CLK_DIV_FSYS3_OFFSET   0xC54C
 
+#define CLK_SRC_CAM_OFFSET     0xC220
+#define CLK_SRC_TV_OFFSET      0xC224
+#define CLK_SRC_MFC_OFFSET     0xC228
+#define CLK_SRC_G3D_OFFSET     0xC22C
+#define CLK_SRC_LCD0_OFFSET    0xC234
 #define CLK_SRC_PERIL0_OFFSET  0xC250
+
+#define CLK_DIV_CAM_OFFSET     0xC520
+#define CLK_DIV_TV_OFFSET      0xC524
+#define CLK_DIV_MFC_OFFSET     0xC528
+#define CLK_DIV_G3D_OFFSET     0xC52C
+#define CLK_DIV_LCD0_OFFSET    0xC534
 #define CLK_DIV_PERIL0_OFFSET  0xC550
 
+#define CLK_SRC_LCD0_OFFSET    0xC234
+
 #define APLL_LOCK_OFFSET       0x14000
 #define MPLL_LOCK_OFFSET       0x14008
 #define APLL_CON0_OFFSET       0x14100
@@ -98,8 +111,8 @@
 #define INFORM1_OFFSET                 0x804
 
 /* GPIO Offsets for UART: GPIO Contol Register */
-#define S5PC210_GPIO_A0_CON_OFFSET     0x00
-#define S5PC210_GPIO_A1_CON_OFFSET     0x20
+#define EXYNOS4_GPIO_A0_CON_OFFSET     0x00
+#define EXYNOS4_GPIO_A1_CON_OFFSET     0x20
 
 /* UART Register offsets */
 #define ULCON_OFFSET           0x00
@@ -108,19 +121,6 @@
 #define UBRDIV_OFFSET          0x28
 #define UFRACVAL_OFFSET                0x2C
 
-/* TZPC : Register Offsets */
-#define TZPC0_BASE             0x10110000
-#define TZPC1_BASE             0x10120000
-#define TZPC2_BASE             0x10130000
-#define TZPC3_BASE             0x10140000
-#define TZPC4_BASE             0x10150000
-#define TZPC5_BASE             0x10160000
-
-#define TZPC_DECPROT0SET_OFFSET        0x804
-#define TZPC_DECPROT1SET_OFFSET        0x810
-#define TZPC_DECPROT2SET_OFFSET        0x81C
-#define TZPC_DECPROT3SET_OFFSET        0x828
-
 /* CLK_SRC_CPU */
 #define MUX_HPM_SEL_MOUTAPLL           0x0
 #define MUX_HPM_SEL_SCLKMPLL           0x1
@@ -351,6 +351,79 @@
                                | (UART1_RATIO << 4) \
                                | (UART0_RATIO << 0))
 
+/* Clock Source CAM/FIMC */
+/* CLK_SRC_CAM */
+#define CAM0_SEL_XUSBXTI       1
+#define CAM1_SEL_XUSBXTI       1
+#define CSIS0_SEL_XUSBXTI      1
+#define CSIS1_SEL_XUSBXTI      1
+
+#define FIMC_SEL_SCLKMPLL      6
+#define FIMC0_LCLK_SEL         FIMC_SEL_SCLKMPLL
+#define FIMC1_LCLK_SEL         FIMC_SEL_SCLKMPLL
+#define FIMC2_LCLK_SEL         FIMC_SEL_SCLKMPLL
+#define FIMC3_LCLK_SEL         FIMC_SEL_SCLKMPLL
+
+#define CLK_SRC_CAM_VAL                ((CSIS1_SEL_XUSBXTI << 28) \
+                               | (CSIS0_SEL_XUSBXTI << 24) \
+                               | (CAM1_SEL_XUSBXTI << 20) \
+                               | (CAM0_SEL_XUSBXTI << 16) \
+                               | (FIMC3_LCLK_SEL << 12) \
+                               | (FIMC2_LCLK_SEL << 8) \
+                               | (FIMC1_LCLK_SEL << 4) \
+                               | (FIMC0_LCLK_SEL << 0))
+
+/* SCLK CAM */
+/* CLK_DIV_CAM */
+#define FIMC0_LCLK_RATIO       4
+#define FIMC1_LCLK_RATIO       4
+#define FIMC2_LCLK_RATIO       4
+#define FIMC3_LCLK_RATIO       4
+#define CLK_DIV_CAM_VAL                ((FIMC3_LCLK_RATIO << 12) \
+                               | (FIMC2_LCLK_RATIO << 8) \
+                               | (FIMC1_LCLK_RATIO << 4) \
+                               | (FIMC0_LCLK_RATIO << 0))
+
+/* SCLK MFC */
+/* CLK_SRC_MFC */
+#define MFC_SEL_MPLL           0
+#define MOUTMFC_0              0
+#define MFC_SEL                        MOUTMFC_0
+#define MFC_0_SEL              MFC_SEL_MPLL
+#define CLK_SRC_MFC_VAL                ((MFC_SEL << 8) | (MFC_0_SEL))
+
+
+/* CLK_DIV_MFC */
+#define MFC_RATIO              3
+#define CLK_DIV_MFC_VAL                (MFC_RATIO)
+
+/* SCLK G3D */
+/* CLK_SRC_G3D */
+#define G3D_SEL_MPLL           0
+#define MOUTG3D_0              0
+#define G3D_SEL                        MOUTG3D_0
+#define G3D_0_SEL              G3D_SEL_MPLL
+#define CLK_SRC_G3D_VAL                ((G3D_SEL << 8) | (G3D_0_SEL))
+
+/* CLK_DIV_G3D */
+#define G3D_RATIO              1
+#define CLK_DIV_G3D_VAL                (G3D_RATIO)
+
+/* SCLK LCD0 */
+/* CLK_SRC_LCD0 */
+#define FIMD_SEL_SCLKMPLL      6
+#define MDNIE0_SEL_XUSBXTI     1
+#define MDNIE_PWM0_SEL_XUSBXTI 1
+#define MIPI0_SEL_XUSBXTI      1
+#define CLK_SRC_LCD0_VAL       ((MIPI0_SEL_XUSBXTI << 12) \
+                               | (MDNIE_PWM0_SEL_XUSBXTI << 8) \
+                               | (MDNIE0_SEL_XUSBXTI << 4) \
+                               | (FIMD_SEL_SCLKMPLL << 0))
+
+/* CLK_DIV_LCD0 */
+#define FIMD0_RATIO            4
+#define CLK_DIV_LCD0_VAL       (FIMD0_RATIO)
+
 /* Required period to generate a stable clock output */
 /* PLL_LOCK_TIME */
 #define PLL_LOCKTIME           0x1C20
@@ -416,8 +489,8 @@
  * UART GPIO_A0/GPIO_A1 Control Register Value
  * 0x2: UART Function
  */
-#define S5PC210_GPIO_A0_CON_VAL        0x22222222
-#define S5PC210_GPIO_A1_CON_VAL        0x222222
+#define EXYNOS4_GPIO_A0_CON_VAL        0x22222222
+#define EXYNOS4_GPIO_A1_CON_VAL        0x222222
 
 /* ULCON: UART Line Control Value 8N1 */
 #define WORD_LEN_5_BIT         0x00
@@ -531,16 +604,4 @@
  * UBRFRACVAL = ((((800MHz*10/(115200*16) -10))%10)*16/10)
  */
 #define UFRACVAL_VAL           0x4
-
-/*
- * TZPC Register Value :
- * R0SIZE: 0x0 : Size of secured ram
- */
-#define R0SIZE                 0x0
-
-/*
- * TZPC Decode Protection Register Value :
- * DECPROTXSET: 0xFF : Set Decode region to non-secure
- */
-#define DECPROTXSET            0xFF
 #endif