Merge branch 'master' of git://www.denx.de/git/u-boot-cfi-flash

[karo-tx-uboot.git] / board / socrates / sdram.c

diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c
index 329eaccd5dba38f4976210ff68a69b595dbc27b6..313efae90f0cacc71fbd5c4b6d97b7f27531a14a 100644 (file)
--- a/board/socrates/sdram.c
+++ b/board/socrates/sdram.c
@@ -2,29 +2,13 @@
  * (C) Copyright 2008
  * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
-
 #include <common.h>
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
 #include <asm/processor.h>
 #include <asm/mmu.h>
 #include <spd_sdram.h>
@@ -38,9 +22,9 @@
  *       so this should be extended for other future boards
  *       using this routine!
  */
-long int sdram_setup(int casl)
+phys_size_t fixed_sdram(void)
 {
-       volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
+       volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
 
        /*
         * Disable memory controller.
@@ -48,50 +32,39 @@ long int sdram_setup(int casl)
        ddr->cs0_config = 0;
        ddr->sdram_cfg = 0;
 
-       ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
-       ddr->cs0_config = CFG_DDR_CS0_CONFIG;
-       ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
-       ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
-       ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
-       ddr->sdram_mode = CFG_DDR_MODE;
-       ddr->sdram_interval = CFG_DDR_INTERVAL;
-       ddr->sdram_cfg_2 = CFG_DDR_CONFIG_2;
-       ddr->sdram_clk_cntl = CFG_DDR_CLK_CONTROL;
+       ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+       ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+       ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+       ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+       ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+       ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
+       ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+       ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONFIG_2;
+       ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CONTROL;
 
        asm ("sync;isync;msync");
        udelay(1000);
 
-       ddr->sdram_cfg = CFG_DDR_CONFIG;
+       ddr->sdram_cfg = CONFIG_SYS_DDR_CONFIG;
        asm ("sync; isync; msync");
        udelay(1000);
 
-       if (get_ram_size(0, CFG_SDRAM_SIZE<<20) == CFG_SDRAM_SIZE<<20) {
+       if (get_ram_size(0, CONFIG_SYS_SDRAM_SIZE<<20) == CONFIG_SYS_SDRAM_SIZE<<20) {
                /*
                 * OK, size detected -> all done
                 */
-               return CFG_SDRAM_SIZE<<20;
+               return CONFIG_SYS_SDRAM_SIZE<<20;
        }
 
        return 0;                               /* nothing found !              */
 }
 #endif
 
-long int initdram (int board_type)
-{
-       long dram_size = 0;
-#if defined(CONFIG_SPD_EEPROM)
-       dram_size = spd_sdram ();
-#else
-       dram_size = sdram_setup(CONFIG_DDR_DEFAULT_CL);
-#endif
-       return dram_size;
-}
-
-#if defined(CFG_DRAM_TEST)
+#if defined(CONFIG_SYS_DRAM_TEST)
 int testdram (void)
 {
-       uint *pstart = (uint *) CFG_MEMTEST_START;
-       uint *pend = (uint *) CFG_MEMTEST_END;
+       uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+       uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
        uint *p;
 
        printf ("SDRAM test phase 1:\n");