Merge branch 'master' of git://git.denx.de/u-boot-video

[karo-tx-uboot.git] / board / ti / beagle / beagle.c

diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index f20ebed4524298c4d5bb777dd732f7ae509d1b1c..c686f40a93398c0c84231a2f6b0463d88f8259ac 100644 (file)
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -72,6 +72,7 @@
 #define BBTOYS_LCD                     0x03000B00
 #define BCT_BRETTL3                    0x01000F00
 #define BCT_BRETTL4                    0x02000F00
+#define LSR_COM6L_ADPT                 0x01001300
 #define BEAGLE_NO_EEPROM               0xffffffff
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -107,13 +108,14 @@ int board_init(void)
 /*
  * Routine: get_board_revision
  * Description: Detect if we are running on a Beagle revision Ax/Bx,
- *             C1/2/3, C4 or xM. This can be done by reading
+ *             C1/2/3, C4, xM Ax/Bx or xM Cx. This can be done by reading
  *             the level of GPIO173, GPIO172 and GPIO171. This should
  *             result in
  *             GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx
  *             GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3
  *             GPIO173, GPIO172, GPIO171: 1 0 1 => C4
- *             GPIO173, GPIO172, GPIO171: 0 0 0 => xM
+ *             GPIO173, GPIO172, GPIO171: 0 1 0 => xM Cx
+ *             GPIO173, GPIO172, GPIO171: 0 0 0 => xM Ax/Bx
  */
 static int get_board_revision(void)
 {
@@ -144,8 +146,7 @@ static int get_board_revision(void)
  * Description: If we use SPL then there is no x-loader nor config header
  * so we have to setup the DDR timings ourself on both banks.
  */
-void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
-               u32 *mr)
+void get_board_mem_timings(struct board_sdrc_timings *timings)
 {
        int pop_mfr, pop_id;
 
@@ -156,29 +157,29 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
         */
        identify_nand_chip(&pop_mfr, &pop_id);
 
-       *mr = MICRON_V_MR_165;
+       timings->mr = MICRON_V_MR_165;
        switch (get_board_revision()) {
        case REVISION_C4:
                if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) {
                        /* 512MB DDR */
-                       *mcfg = NUMONYX_V_MCFG_165(512 << 20);
-                       *ctrla = NUMONYX_V_ACTIMA_165;
-                       *ctrlb = NUMONYX_V_ACTIMB_165;
-                       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+                       timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
+                       timings->ctrla = NUMONYX_V_ACTIMA_165;
+                       timings->ctrlb = NUMONYX_V_ACTIMB_165;
+                       timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
                        break;
                } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xba) {
                        /* Beagleboard Rev C4, 512MB Nand/256MB DDR*/
-                       *mcfg = MICRON_V_MCFG_165(128 << 20);
-                       *ctrla = MICRON_V_ACTIMA_165;
-                       *ctrlb = MICRON_V_ACTIMB_165;
-                       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+                       timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+                       timings->ctrla = MICRON_V_ACTIMA_165;
+                       timings->ctrlb = MICRON_V_ACTIMB_165;
+                       timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
                        break;
                } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) {
                        /* Beagleboard Rev C5, 256MB DDR */
-                       *mcfg = MICRON_V_MCFG_200(256 << 20);
-                       *ctrla = MICRON_V_ACTIMA_200;
-                       *ctrlb = MICRON_V_ACTIMB_200;
-                       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+                       timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+                       timings->ctrla = MICRON_V_ACTIMA_200;
+                       timings->ctrlb = MICRON_V_ACTIMB_200;
+                       timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
                        break;
                }
        case REVISION_XM_A:
@@ -186,24 +187,24 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
        case REVISION_XM_C:
                if (pop_mfr == 0) {
                        /* 256MB DDR */
-                       *mcfg = MICRON_V_MCFG_200(256 << 20);
-                       *ctrla = MICRON_V_ACTIMA_200;
-                       *ctrlb = MICRON_V_ACTIMB_200;
-                       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+                       timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+                       timings->ctrla = MICRON_V_ACTIMA_200;
+                       timings->ctrlb = MICRON_V_ACTIMB_200;
+                       timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
                } else {
                        /* 512MB DDR */
-                       *mcfg = NUMONYX_V_MCFG_165(512 << 20);
-                       *ctrla = NUMONYX_V_ACTIMA_165;
-                       *ctrlb = NUMONYX_V_ACTIMB_165;
-                       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+                       timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
+                       timings->ctrla = NUMONYX_V_ACTIMA_165;
+                       timings->ctrlb = NUMONYX_V_ACTIMB_165;
+                       timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
                }
                break;
        default:
                /* Assume 128MB and Micron/165MHz timings to be safe */
-               *mcfg = MICRON_V_MCFG_165(128 << 20);
-               *ctrla = MICRON_V_ACTIMA_165;
-               *ctrlb = MICRON_V_ACTIMB_165;
-               *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+               timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+               timings->ctrla = MICRON_V_ACTIMA_165;
+               timings->ctrlb = MICRON_V_ACTIMB_165;
+               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
        }
 }
 #endif
@@ -228,6 +229,14 @@ static unsigned int get_expansion_id(void)
        i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config,
                 sizeof(expansion_config));
 
+       /* retry reading configuration data with 16bit addressing */
+       if ((expansion_config.device_vendor == 0xFFFFFF00) ||
+           (expansion_config.device_vendor == 0xFFFFFFFF)) {
+               printf("EEPROM is blank or 8bit addressing failed: retrying with 16bit:\n");
+               i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 2, (u8 *)&expansion_config,
+                        sizeof(expansion_config));
+       }
+
        i2c_set_bus_num(TWL4030_I2C_BUS);
 
        return expansion_config.device_vendor;
@@ -455,6 +464,11 @@ int misc_init_r(void)
        case BCT_BRETTL4:
                printf("Recognized bct electronic GmbH brettl4 board\n");
                break;
+       case LSR_COM6L_ADPT:
+               printf("Recognized LSR COM6L Adapter Board\n");
+               MUX_BBTOYS_WIFI()
+               setenv("buddy", "lsr-com6l-adpt");
+               break;
        case BEAGLE_NO_EEPROM:
                printf("No EEPROM on expansion board\n");
                setenv("buddy", "none");
@@ -519,8 +533,7 @@ void set_muxconf_regs(void)
 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
 int board_mmc_init(bd_t *bis)
 {
-       omap_mmc_init(0, 0, 0);
-       return 0;
+       return omap_mmc_init(0, 0, 0, -1, -1);
 }
 #endif