*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
-#include <asm/immap_fsl_pci.h>
+#include <asm/fsl_pci.h>
#include <asm/io.h>
+#include <linux/compiler.h>
#include <ioports.h>
#include <flash.h>
#include <libfdt.h>
int misc_init_r (void)
{
- volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
-
/*
* Adjust flash start and offset to detected values
*/
* Recalculate CS configuration if second FLASH bank is available
*/
if (flash_info[0].size > 0) {
- memctl->or1 = ((-flash_info[0].size) & 0xffff8000) |
- (CONFIG_SYS_OR1_PRELIM & 0x00007fff);
- memctl->br1 = gd->bd->bi_flashstart |
- (CONFIG_SYS_BR1_PRELIM & 0x00007fff);
+ set_lbc_or(1, ((-flash_info[0].size) & 0xffff8000) |
+ (CONFIG_SYS_OR1_PRELIM & 0x00007fff));
+ set_lbc_br(1, gd->bd->bi_flashstart |
+ (CONFIG_SYS_BR1_PRELIM & 0x00007fff));
/*
* Re-check to get correct base address for bank 1
*/
flash_get_size (gd->bd->bi_flashstart, 0);
} else {
- memctl->or1 = 0;
- memctl->br1 = 0;
+ set_lbc_or(1, 0);
+ set_lbc_br(1, 0);
}
/*
* If bank 1 is equipped, bank 0 is mapped after bank 1
*/
- memctl->or0 = ((-flash_info[1].size) & 0xffff8000) |
- (CONFIG_SYS_OR0_PRELIM & 0x00007fff);
- memctl->br0 = (gd->bd->bi_flashstart + flash_info[0].size) |
- (CONFIG_SYS_BR0_PRELIM & 0x00007fff);
+ set_lbc_or(0, ((-flash_info[1].size) & 0xffff8000) |
+ (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
+ set_lbc_br(0, gd->bd->bi_flashstart |
+ (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
+
/*
* Re-check to get correct base address for bank 0
*/
/* Monitor protection ON by default */
flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+ CONFIG_SYS_MONITOR_BASE, 0xffffffff,
&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
/* Environment protection ON by default */
/* Redundant environment protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CONFIG_ENV_ADDR_REDUND,
- CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1,
+ CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
#endif
*/
static void upmc_write (u_char addr, uint val)
{
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
out_be32 (&lbc->mdr, val);
uint get_lbc_clock (void)
{
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
sys_info_t sys_info;
- ulong clkdiv = lbc->lcrr & 0x0f;
+ ulong clkdiv = lbc->lcrr & LCRR_CLKDIV;
get_sys_info (&sys_info);
void local_bus_init (void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint lbc_mhz = get_lbc_clock () / 1000000;
#ifdef CONFIG_MPC8548
* Errata LBC11.
* Fix Local Bus clock glitch when DLL is enabled.
*
- * If localbus freq is < 66Mhz, DLL bypass mode must be used.
- * If localbus freq is > 133Mhz, DLL can be safely enabled.
+ * If localbus freq is < 66MHz, DLL bypass mode must be used.
+ * If localbus freq is > 133MHz, DLL can be safely enabled.
* Between 66 and 133, the DLL is enabled with an override workaround.
*/
* set if Local Bus Clock is > 83 MHz.
*/
if (lbc_mhz > 83)
- out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD);
+ set_lbc_or(2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD);
else
- out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN);
- out_be32 (&lbc->br2, CONFIG_SYS_BR2_CAN);
+ set_lbc_or(2, CONFIG_SYS_OR2_CAN);
+ set_lbc_br(2, CONFIG_SYS_BR2_CAN);
/* LGPL4 is UPWAIT */
out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X);
/*
* Initialize PCI Devices, report devices found.
*/
-static int first_free_busno;
-#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
+#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
-#endif /* CONFIG_PCI || CONFIG_PCI1 */
+#endif /* CONFIG_PCI1 */
#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif /* CONFIG_PCIE1 */
-static inline void init_pci1(void)
+void pci_init_board (void)
{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
- uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCI1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
- struct pci_controller *hose = &pci1_hose;
-
- /* PORDEVSR[15] */
- uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
- /* PORDEVSR[14] */
- uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
- /* PORPLLSR[16] */
- uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
-
- uint pci_agent = (host_agent == 3) || (host_agent == 4 ) ||
- (host_agent == 6);
+ struct fsl_pci_info pci_info[2];
+ int first_free_busno = 0;
+ int num = 0;
+ int pcie_ep;
+ __maybe_unused int pcie_configured;
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 devdisr = in_be32(&gur->devdisr);
+ u32 pordevsr = in_be32(&gur->pordevsr);
+ __maybe_unused uint io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+ MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+
+#ifdef CONFIG_PCI1
+ uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32;
+ uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB;
uint pci_speed = CONFIG_SYS_CLK_FREQ; /* PCI PSPEED in [4:5] */
+ uint pci_clk_sel = in_be32(&gur->porpllsr) & MPC85xx_PORDEVSR_PCI1_SPD;
- if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
- printf ("PCI1: %d bit, %s MHz, %s, %s, %s\n",
+ if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+ SET_STD_PCI_INFO(pci_info[num], 1);
+ pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
+ printf ("\n PCI1: %d bit, %s MHz, %s, %s, %s\n",
(pci_32) ? 32 : 64,
(pci_speed == 33333333) ? "33" :
(pci_speed == 66666666) ? "66" : "unknown",
pci_clk_sel ? "sync" : "async",
- pci_agent ? "agent" : "host",
+ pcie_ep ? "agent" : "host",
pci_arb ? "arbiter" : "external-arbiter");
-
-
- /* inbound */
- pci_set_region (hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
-
-
- /* outbound memory */
- pci_set_region (hose->regions + 1,
- CONFIG_SYS_PCI1_MEM_BASE,
- CONFIG_SYS_PCI1_MEM_PHYS,
- CONFIG_SYS_PCI1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region (hose->regions + 2,
- CONFIG_SYS_PCI1_IO_BASE,
- CONFIG_SYS_PCI1_IO_PHYS,
- CONFIG_SYS_PCI1_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = 3;
-
- hose->first_busno = first_free_busno;
- pci_setup_indirect (hose, (int)&pci->cfg_addr,
- (int)&pci->cfg_data);
-
- fsl_pci_init (hose);
-
- printf (" PCI on bus %02x..%02x\n",
- hose->first_busno, hose->last_busno);
-
- first_free_busno = hose->last_busno + 1;
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pci1_hose, first_free_busno);
#ifdef CONFIG_PCIX_CHECK
- if (!(gur->pordevsr & PORDEVSR_PCI)) {
+ if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1)) {
ushort reg16 =
PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ |
PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
- uint dev = PCI_BDF(hose->first_busno, 0, 0);
+ uint dev = PCI_BDF(0, 0, 0);
/* PCI-X init */
if (CONFIG_SYS_CLK_FREQ < 66000000)
puts ("PCI-X will only work at 66 MHz\n");
- pci_hose_write_config_word (hose, dev, PCIX_COMMAND,
- reg16);
+ pci_write_config_word(dev, PCIX_COMMAND, reg16);
}
#endif
} else {
- puts ("PCI1: disabled\n");
+ printf(" PCI1: disabled\n");
}
-#else /* !(CONFIG_PCI || CONFIG_PCI1) */
- gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
-#endif /* CONFIG_PCI || CONFIG_PCI1) */
-}
+#else
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
+#endif
-static inline void init_pcie1(void)
-{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_PCIE1
- uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCIE1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
- struct pci_controller *hose = &pcie1_hose;
- int pcie_ep = (host_agent == 0) || (host_agent == 2 ) ||
- (host_agent == 3);
-
- int pcie_configured = io_sel >= 1;
-
- if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
- printf ("PCIe: %s, base address %x",
- pcie_ep ? "End point" : "Root complex", (uint)pci);
-
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug (", with errors. Clearing. Now 0x%08x",
- pci->pme_msg_det);
- }
- puts ("\n");
-
- /* inbound */
- pci_set_region (hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
-
- /* outbound memory */
- pci_set_region (hose->regions + 1,
- CONFIG_SYS_PCIE1_MEM_BASE,
- CONFIG_SYS_PCIE1_MEM_PHYS,
- CONFIG_SYS_PCIE1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region (hose->regions + 2,
- CONFIG_SYS_PCIE1_IO_BASE,
- CONFIG_SYS_PCIE1_IO_PHYS,
- CONFIG_SYS_PCIE1_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = 3;
-
- hose->first_busno = first_free_busno;
- pci_setup_indirect(hose, (int)&pci->cfg_addr,
- (int)&pci->cfg_data);
-
- fsl_pci_init (hose);
- printf (" PCIe on bus %02x..%02x\n",
- hose->first_busno, hose->last_busno);
-
- first_free_busno = hose->last_busno + 1;
-
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
+
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
+ SET_STD_PCIE_INFO(pci_info[num], 1);
+ pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
+ printf(" PCIE1 connected as %s\n",
+ pcie_ep ? "Endpoint" : "Root Complex");
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie1_hose, first_free_busno);
} else {
- printf ("PCIe: disabled\n");
+ printf(" PCIE1: disabled\n");
}
-#else /* !CONFIG_PCIE1 */
- gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+#else
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE);
#endif /* CONFIG_PCIE1 */
}
-void pci_init_board (void)
-{
- init_pci1();
- init_pcie1();
-}
-
#ifdef CONFIG_OF_BOARD_SETUP
void ft_board_setup (void *blob, bd_t *bd)
{
- int node, tmp[2];
- const char *path;
-
ft_cpu_setup (blob, bd);
- node = fdt_path_offset (blob, "/aliases");
- tmp[0] = 0;
- if (node >= 0) {
-#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
- path = fdt_getprop (blob, node, "pci0", NULL);
- if (path) {
- tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
- do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1);
- }
-#endif /* CONFIG_PCI || CONFIG_PCI1 */
-#ifdef CONFIG_PCIE1
- path = fdt_getprop (blob, node, "pci1", NULL);
- if (path) {
- tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
- do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1);
- }
-#endif /* CONFIG_PCIE1 */
- }
+ FT_FSL_PCI_SETUP;
}
#endif /* CONFIG_OF_BOARD_SETUP */
projects / karo-tx-uboot.git / blobdiff