imported Ka-Ro specific additions to U-Boot 2009.08 for TX28

[karo-tx-uboot.git] / board / xaeniax / lowlevel_init.S

diff --git a/board/xaeniax/lowlevel_init.S b/board/xaeniax/lowlevel_init.S
index fe3e7128a4bfd7b41faa80124445bcd909c00619..57e16200501a6ec2a55bf77d32ff98d1a3932d6c 100755 (executable)
--- a/board/xaeniax/lowlevel_init.S
+++ b/board/xaeniax/lowlevel_init.S
@@ -29,7 +29,7 @@
 #include <version.h>
 #include <asm/arch/pxa-regs.h>
 
-DRAM_SIZE:  .long   CFG_DRAM_SIZE
+DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
 
 /* wait for coprocessor write complete */
        .macro CPWAIT reg
@@ -47,67 +47,67 @@ lowlevel_init:
        /* Set up GPIO pins first ----------------------------------------- */
 
        ldr     r0,=GPSR0
-       ldr     r1,=CFG_GPSR0_VAL
+       ldr     r1,=CONFIG_SYS_GPSR0_VAL
        str     r1,[r0]
 
        ldr     r0,=GPSR1
-       ldr     r1,=CFG_GPSR1_VAL
+       ldr     r1,=CONFIG_SYS_GPSR1_VAL
        str     r1,[r0]
 
        ldr     r0,=GPSR2
-       ldr     r1,=CFG_GPSR2_VAL
+       ldr     r1,=CONFIG_SYS_GPSR2_VAL
        str     r1,[r0]
 
        ldr     r0,=GPCR0
-       ldr     r1,=CFG_GPCR0_VAL
+       ldr     r1,=CONFIG_SYS_GPCR0_VAL
        str     r1,[r0]
 
        ldr     r0,=GPCR1
-       ldr     r1,=CFG_GPCR1_VAL
+       ldr     r1,=CONFIG_SYS_GPCR1_VAL
        str     r1,[r0]
 
        ldr     r0,=GPCR2
-       ldr     r1,=CFG_GPCR2_VAL
+       ldr     r1,=CONFIG_SYS_GPCR2_VAL
        str     r1,[r0]
 
        ldr     r0,=GPDR0
-       ldr     r1,=CFG_GPDR0_VAL
+       ldr     r1,=CONFIG_SYS_GPDR0_VAL
        str     r1,[r0]
 
        ldr     r0,=GPDR1
-       ldr     r1,=CFG_GPDR1_VAL
+       ldr     r1,=CONFIG_SYS_GPDR1_VAL
        str     r1,[r0]
 
        ldr     r0,=GPDR2
-       ldr     r1,=CFG_GPDR2_VAL
+       ldr     r1,=CONFIG_SYS_GPDR2_VAL
        str     r1,[r0]
 
        ldr     r0,=GAFR0_L
-       ldr     r1,=CFG_GAFR0_L_VAL
+       ldr     r1,=CONFIG_SYS_GAFR0_L_VAL
        str     r1,[r0]
 
        ldr     r0,=GAFR0_U
-       ldr     r1,=CFG_GAFR0_U_VAL
+       ldr     r1,=CONFIG_SYS_GAFR0_U_VAL
        str     r1,[r0]
 
        ldr     r0,=GAFR1_L
-       ldr     r1,=CFG_GAFR1_L_VAL
+       ldr     r1,=CONFIG_SYS_GAFR1_L_VAL
        str     r1,[r0]
 
        ldr     r0,=GAFR1_U
-       ldr     r1,=CFG_GAFR1_U_VAL
+       ldr     r1,=CONFIG_SYS_GAFR1_U_VAL
        str     r1,[r0]
 
        ldr     r0,=GAFR2_L
-       ldr     r1,=CFG_GAFR2_L_VAL
+       ldr     r1,=CONFIG_SYS_GAFR2_L_VAL
        str     r1,[r0]
 
        ldr     r0,=GAFR2_U
-       ldr     r1,=CFG_GAFR2_U_VAL
+       ldr     r1,=CONFIG_SYS_GAFR2_U_VAL
        str     r1,[r0]
 
        ldr     r0,=PSSR                /* enable GPIO pins */
-       ldr     r1,=CFG_PSSR_VAL
+       ldr     r1,=CONFIG_SYS_PSSR_VAL
        str     r1,[r0]
 
        /* ---------------------------------------------------------------- */
@@ -145,17 +145,17 @@ mem_init:
        /* MSC registers: timing, bus width, mem type                       */
 
        /* MSC0: nCS(0,1)                                                   */
-       ldr     r2,=CFG_MSC0_VAL
+       ldr     r2,=CONFIG_SYS_MSC0_VAL
        str     r2,[r1, #MSC0_OFFSET]
        ldr     r2,[r1, #MSC0_OFFSET]   /* read back to ensure data latches */
 
        /* MSC1: nCS(2,3)                                                   */
-       ldr     r2,=CFG_MSC1_VAL
+       ldr     r2,=CONFIG_SYS_MSC1_VAL
        str     r2,[r1, #MSC1_OFFSET]
        ldr     r2,[r1, #MSC1_OFFSET]
 
        /* MSC2: nCS(4,5)                                                   */
-       ldr     r2,=CFG_MSC2_VAL
+       ldr     r2,=CONFIG_SYS_MSC2_VAL
        str     r2,[r1, #MSC2_OFFSET]
        ldr     r2,[r1, #MSC2_OFFSET]
 
@@ -164,37 +164,37 @@ mem_init:
        /* ---------------------------------------------------------------- */
 
        /* MECR: Memory Expansion Card Register                             */
-       ldr     r2,=CFG_MECR_VAL
+       ldr     r2,=CONFIG_SYS_MECR_VAL
        str     r2,[r1, #MECR_OFFSET]
        ldr     r2,[r1, #MECR_OFFSET]
 
        /* MCMEM0: Card Interface slot 0 timing                             */
-       ldr     r2,=CFG_MCMEM0_VAL
+       ldr     r2,=CONFIG_SYS_MCMEM0_VAL
        str     r2,[r1, #MCMEM0_OFFSET]
        ldr     r2,[r1, #MCMEM0_OFFSET]
 
        /* MCMEM1: Card Interface slot 1 timing                             */
-       ldr     r2,=CFG_MCMEM1_VAL
+       ldr     r2,=CONFIG_SYS_MCMEM1_VAL
        str     r2,[r1, #MCMEM1_OFFSET]
        ldr     r2,[r1, #MCMEM1_OFFSET]
 
        /* MCATT0: Card Interface Attribute Space Timing, slot 0            */
-       ldr     r2,=CFG_MCATT0_VAL
+       ldr     r2,=CONFIG_SYS_MCATT0_VAL
        str     r2,[r1, #MCATT0_OFFSET]
        ldr     r2,[r1, #MCATT0_OFFSET]
 
        /* MCATT1: Card Interface Attribute Space Timing, slot 1            */
-       ldr     r2,=CFG_MCATT1_VAL
+       ldr     r2,=CONFIG_SYS_MCATT1_VAL
        str     r2,[r1, #MCATT1_OFFSET]
        ldr     r2,[r1, #MCATT1_OFFSET]
 
        /* MCIO0: Card Interface I/O Space Timing, slot 0                   */
-       ldr     r2,=CFG_MCIO0_VAL
+       ldr     r2,=CONFIG_SYS_MCIO0_VAL
        str     r2,[r1, #MCIO0_OFFSET]
        ldr     r2,[r1, #MCIO0_OFFSET]
 
        /* MCIO1: Card Interface I/O Space Timing, slot 1                   */
-       ldr     r2,=CFG_MCIO1_VAL
+       ldr     r2,=CONFIG_SYS_MCIO1_VAL
        str     r2,[r1, #MCIO1_OFFSET]
        ldr     r2,[r1, #MCIO1_OFFSET]
 
@@ -207,7 +207,7 @@ mem_init:
        /* ---------------------------------------------------------------- */
 
        @ get the mdrefr settings
-       ldr     r4,=CFG_MDREFR_VAL
+       ldr     r4,=CONFIG_SYS_MDREFR_VAL
 
        @ write back mdrefr
        str     r4,[r1, #MDREFR_OFFSET]
@@ -261,7 +261,7 @@ mem_init:
        /* Step 4d:                                                     */
        /* fetch platform value of mdcnfg                               */
        @
-       ldr     r2,  =CFG_MDCNFG_VAL
+       ldr     r2,  =CONFIG_SYS_MDCNFG_VAL
 
        @ disable all sdram banks
        @
@@ -296,7 +296,7 @@ mem_init:
        /*          documented in SDRAM data sheets. The address(es) used   */
        /*          for this purpose must not be cacheable.                 */
 
-       ldr     r3,     =CFG_DRAM_BASE
+       ldr     r3,     =CONFIG_SYS_DRAM_BASE
        str     r2,     [r3]
        str     r2,     [r3]
        str     r2,     [r3]
@@ -326,7 +326,7 @@ mem_init:
 
        /* Step 4h: Write MDMRS.                                            */
 
-       ldr     r2,     =CFG_MDMRS_VAL
+       ldr     r2,     =CONFIG_SYS_MDMRS_VAL
        str     r2,     [r1, #MDMRS_OFFSET]
 
 
@@ -342,7 +342,7 @@ initirqs:
        ldr     r2,  =ICLR
        str     r1,  [r2]
 
-       ldr     r1,  =CFG_ICMR_VAL /* mask all interrupts at the controller */
+       ldr     r1,  =CONFIG_SYS_ICMR_VAL /* mask all interrupts at the controller */
        ldr     r2,  =ICMR
        str     r1,  [r2]
 
@@ -388,7 +388,7 @@ initclks:
        @
 test:
        ldr     r1,  =CKEN
-       ldr     r2,  =CFG_CKEN_VAL
+       ldr     r2,  =CONFIG_SYS_CKEN_VAL
        str     r2,  [r1]
 
        /* ---------------------------------------------------------------- */