#include <version.h>
#include <environment.h>
#include <fdtdec.h>
+#include <fs.h>
+#if defined(CONFIG_CMD_IDE)
+#include <ide.h>
+#endif
+#include <i2c.h>
#include <initcall.h>
#include <logbuff.h>
+
+/* TODO: Can we move these into arch/ headers? */
+#ifdef CONFIG_8xx
+#include <mpc8xx.h>
+#endif
+#ifdef CONFIG_5xx
+#include <mpc5xx.h>
+#endif
+#ifdef CONFIG_MPC5xxx
+#include <mpc5xxx.h>
+#endif
+
+#include <os.h>
#include <post.h>
+#include <spi.h>
+#include <watchdog.h>
+#include <asm/errno.h>
#include <asm/io.h>
+#ifdef CONFIG_MP
+#include <asm/mp.h>
+#endif
#include <asm/sections.h>
+#ifdef CONFIG_X86
+#include <asm/init_helpers.h>
+#include <asm/relocate.h>
+#endif
+#ifdef CONFIG_SANDBOX
+#include <asm/state.h>
+#endif
#include <linux/compiler.h>
/*
* Could the CONFIG_SPL_BUILD infection become a flag in gd?
*/
+#if defined(CONFIG_WATCHDOG)
+static int init_func_watchdog_init(void)
+{
+ puts(" Watchdog enabled\n");
+ WATCHDOG_RESET();
+
+ return 0;
+}
+
+int init_func_watchdog_reset(void)
+{
+ WATCHDOG_RESET();
+
+ return 0;
+}
+#endif /* CONFIG_WATCHDOG */
+
+void __board_add_ram_info(int use_default)
+{
+ /* please define platform specific board_add_ram_info() */
+}
+
+void board_add_ram_info(int)
+ __attribute__ ((weak, alias("__board_add_ram_info")));
+
static int init_baud_rate(void)
{
gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
static int display_text_info(void)
{
+#ifndef CONFIG_SANDBOX
ulong bss_start, bss_end;
+#ifdef CONFIG_SYS_SYM_OFFSETS
bss_start = _bss_start_ofs + _TEXT_BASE;
bss_end = _bss_end_ofs + _TEXT_BASE;
+#else
+ bss_start = (ulong)&__bss_start;
+ bss_end = (ulong)&__bss_end;
+#endif
debug("U-Boot code: %08X -> %08lX BSS: -> %08lX\n",
CONFIG_SYS_TEXT_BASE, bss_start, bss_end);
+#endif
#ifdef CONFIG_MODEM_SUPPORT
debug("Modem Support enabled\n");
return 0;
}
+#ifdef CONFIG_PPC
+static int init_func_ram(void)
+{
+#ifdef CONFIG_BOARD_TYPES
+ int board_type = gd->board_type;
+#else
+ int board_type = 0; /* use dummy arg */
+#endif
+
+ gd->ram_size = initdram(board_type);
+
+ if (gd->ram_size > 0)
+ return 0;
+
+ puts("*** failed ***\n");
+ return 1;
+}
+#endif
+
static int show_dram_config(void)
{
ulong size;
size = gd->ram_size;
#endif
- print_size(size, "\n");
+ print_size(size, "");
+ board_add_ram_info(0);
+ putc('\n');
return 0;
}
+ulong get_effective_memsize(void)
+{
+#ifndef CONFIG_VERY_BIG_RAM
+ return gd->ram_size;
+#else
+ /* limit stack to what we can reasonable map */
+ return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
+ CONFIG_MAX_MEM_MAPPED : gd->ram_size);
+#endif
+}
+
void __dram_init_banksize(void)
{
#if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
void dram_init_banksize(void)
__attribute__((weak, alias("__dram_init_banksize")));
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+static int init_func_i2c(void)
+{
+ puts("I2C: ");
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ puts("ready\n");
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_HARD_SPI)
+static int init_func_spi(void)
+{
+ puts("SPI: ");
+ spi_init();
+ puts("ready\n");
+ return 0;
+}
+#endif
+
+__maybe_unused
static int zero_global_data(void)
{
memset((void *)gd, '\0', sizeof(gd_t));
static int setup_mon_len(void)
{
+#ifdef CONFIG_SYS_SYM_OFFSETS
gd->mon_len = _bss_end_ofs;
+#elif defined(CONFIG_SANDBOX)
+ gd->mon_len = (ulong)&_end - (ulong)_init;
+#else
+ /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
+ gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
+#endif
return 0;
}
return 0;
}
+#ifdef CONFIG_OF_HOSTFILE
+
+#define CHECK(x) err = (x); if (err) goto failed;
+
+/* Create an empty device tree blob */
+static int make_empty_fdt(void *fdt)
+{
+ int err;
+
+ CHECK(fdt_create(fdt, 256));
+ CHECK(fdt_finish_reservemap(fdt));
+ CHECK(fdt_begin_node(fdt, ""));
+ CHECK(fdt_end_node(fdt));
+ CHECK(fdt_finish(fdt));
+
+ return 0;
+failed:
+ printf("Unable to create empty FDT: %s\n", fdt_strerror(err));
+ return -EACCES;
+}
+
+static int read_fdt_from_file(void)
+{
+ struct sandbox_state *state = state_get_current();
+ void *blob;
+ int size;
+ int err;
+
+ blob = map_sysmem(CONFIG_SYS_FDT_LOAD_ADDR, 0);
+ if (!state->fdt_fname) {
+ err = make_empty_fdt(blob);
+ if (!err)
+ goto done;
+ return err;
+ }
+ err = fs_set_blk_dev("host", NULL, FS_TYPE_SANDBOX);
+ if (err)
+ return err;
+ size = fs_read(state->fdt_fname, CONFIG_SYS_FDT_LOAD_ADDR, 0, 0);
+ if (size < 0)
+ return -EIO;
+
+done:
+ gd->fdt_blob = blob;
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SANDBOX
+static int setup_ram_buf(void)
+{
+ gd->arch.ram_buf = os_malloc(CONFIG_SYS_SDRAM_SIZE);
+ assert(gd->arch.ram_buf);
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+#endif
+
static int setup_fdt(void)
{
#ifdef CONFIG_OF_EMBED
gd->fdt_blob = _binary_dt_dtb_start;
#elif defined CONFIG_OF_SEPARATE
/* FDT is at end of image */
+# ifdef CONFIG_SYS_SYM_OFFSETS
gd->fdt_blob = (void *)(_end_ofs + CONFIG_SYS_TEXT_BASE);
+# else
+ gd->fdt_blob = (ulong *)&_end;
+# endif
+#elif defined(CONFIG_OF_HOSTFILE)
+ if (read_fdt_from_file()) {
+ puts("Failed to read control FDT\n");
+ return -1;
+ }
#endif
/* Allow the early environment to override the fdt address */
gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16,
#ifdef CONFIG_SYS_SDRAM_BASE
gd->ram_top = CONFIG_SYS_SDRAM_BASE;
#endif
+ gd->ram_top += get_effective_memsize();
gd->ram_top = board_get_usable_ram_top(gd->mon_len);
gd->dest_addr = gd->ram_top;
debug("Ram top: %08lX\n", (ulong)gd->ram_top);
+#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
+ /*
+ * We need to make sure the location we intend to put secondary core
+ * boot code is reserved and not used by any part of u-boot
+ */
+ if (gd->dest_addr > determine_mp_bootpg(NULL)) {
+ gd->dest_addr = determine_mp_bootpg(NULL);
+ debug("Reserving MP boot page to %08lx\n", gd->dest_addr);
+ }
+#endif
gd->dest_addr_sp = gd->dest_addr;
return 0;
}
}
#endif /* CONFIG_LCD */
+#if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) \
+ && !defined(CONFIG_ARM) && !defined(CONFIG_X86)
+static int reserve_video(void)
+{
+ /* reserve memory for video display (always full pages) */
+ gd->dest_addr = video_setmem(gd->dest_addr);
+ gd->fb_base = gd->dest_addr;
+
+ return 0;
+}
+#endif
+
static int reserve_uboot(void)
{
/*
*/
gd->dest_addr -= gd->mon_len;
gd->dest_addr &= ~(4096 - 1);
+#ifdef CONFIG_E500
+ /* round down to next 64 kB limit so that IVPR stays aligned */
+ gd->dest_addr &= ~(65536 - 1);
+#endif
debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10,
gd->dest_addr);
return 0;
}
+#ifndef CONFIG_SPL_BUILD
/* reserve memory for malloc() area */
static int reserve_malloc(void)
{
static int reserve_board(void)
{
gd->dest_addr_sp -= sizeof(bd_t);
- gd->bd = (bd_t *)gd->dest_addr_sp;
+ gd->bd = (bd_t *)map_sysmem(gd->dest_addr_sp, sizeof(bd_t));
memset(gd->bd, '\0', sizeof(bd_t));
debug("Reserving %zu Bytes for Board Info at: %08lx\n",
sizeof(bd_t), gd->dest_addr_sp);
return 0;
}
+#endif
static int setup_machine(void)
{
static int reserve_global_data(void)
{
gd->dest_addr_sp -= sizeof(gd_t);
- gd->new_gd = (gd_t *)gd->dest_addr_sp;
+ gd->new_gd = (gd_t *)map_sysmem(gd->dest_addr_sp, sizeof(gd_t));
debug("Reserving %zu Bytes for Global Data at: %08lx\n",
sizeof(gd_t), gd->dest_addr_sp);
return 0;
gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
gd->dest_addr_sp -= gd->fdt_size;
- gd->new_fdt = (void *)gd->dest_addr_sp;
- debug("Reserving %lu Bytes for FDT at: %p\n",
- gd->fdt_size, gd->new_fdt);
+ gd->new_fdt = map_sysmem(gd->dest_addr_sp, gd->fdt_size);
+ debug("Reserving %lu Bytes for FDT at: %08lx\n",
+ gd->fdt_size, gd->dest_addr_sp);
}
return 0;
static int reserve_stacks(void)
{
+#ifdef CONFIG_SPL_BUILD
+# ifdef CONFIG_ARM
+ gd->dest_addr_sp -= 128; /* leave 32 words for abort-stack */
+ gd->irq_sp = gd->dest_addr_sp;
+# endif
+#else
+# ifdef CONFIG_PPC
+ ulong *s;
+# endif
+
/* setup stack pointer for exceptions */
gd->dest_addr_sp -= 16;
gd->dest_addr_sp &= ~0xf;
# endif
/* leave 3 words for abort-stack, plus 1 for alignment */
gd->dest_addr_sp -= 16;
+# elif defined(CONFIG_PPC)
+ /* Clear initial stack frame */
+ s = (ulong *) gd->dest_addr_sp;
+ *s = 0; /* Terminate back chain */
+ *++s = 0; /* NULL return address */
+# endif /* Architecture specific code */
return 0;
+#endif
}
static int display_new_sp(void)
return 0;
}
+#ifdef CONFIG_PPC
+static int setup_board_part1(void)
+{
+ bd_t *bd = gd->bd;
+
+ /*
+ * Save local variables to board info struct
+ */
+
+ bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */
+ bd->bi_memsize = gd->ram_size; /* size in bytes */
+
+#ifdef CONFIG_SYS_SRAM_BASE
+ bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
+ bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
+#endif
+
+#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \
+ defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+ bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
+#endif
+#if defined(CONFIG_MPC5xxx)
+ bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
+#endif
+#if defined(CONFIG_MPC83xx)
+ bd->bi_immrbar = CONFIG_SYS_IMMR;
+#endif
+
+ return 0;
+}
+
+static int setup_board_part2(void)
+{
+ bd_t *bd = gd->bd;
+
+ bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
+ bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
+#if defined(CONFIG_CPM2)
+ bd->bi_cpmfreq = gd->arch.cpm_clk;
+ bd->bi_brgfreq = gd->arch.brg_clk;
+ bd->bi_sccfreq = gd->arch.scc_clk;
+ bd->bi_vco = gd->arch.vco_out;
+#endif /* CONFIG_CPM2 */
+#if defined(CONFIG_MPC512X)
+ bd->bi_ipsfreq = gd->arch.ips_clk;
+#endif /* CONFIG_MPC512X */
+#if defined(CONFIG_MPC5xxx)
+ bd->bi_ipbfreq = gd->arch.ipb_clk;
+ bd->bi_pcifreq = gd->pci_clk;
+#endif /* CONFIG_MPC5xxx */
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SYS_EXTBDINFO
+static int setup_board_extra(void)
+{
+ bd_t *bd = gd->bd;
+
+ strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version));
+ strncpy((char *) bd->bi_r_version, U_BOOT_VERSION,
+ sizeof(bd->bi_r_version));
+
+ bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */
+ bd->bi_plb_busfreq = gd->bus_clk;
+#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
+ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+ bd->bi_pci_busfreq = get_PCI_freq();
+ bd->bi_opbfreq = get_OPB_freq();
+#elif defined(CONFIG_XILINX_405)
+ bd->bi_pci_busfreq = get_PCI_freq();
+#endif
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_POST
static int init_post(void)
{
memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
debug("Relocation Offset is: %08lx\n", gd->reloc_off);
- debug("Relocating to %08lx, new gd at %p, sp at %08lx\n",
- gd->dest_addr, gd->new_gd, gd->dest_addr_sp);
+ debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
+ gd->dest_addr, (ulong)map_to_sysmem(gd->new_gd),
+ gd->dest_addr_sp);
return 0;
}
static int jump_to_copy(void)
{
+ /*
+ * x86 is special, but in a nice way. It uses a trampoline which
+ * enables the dcache if possible.
+ *
+ * For now, other archs use relocate_code(), which is implemented
+ * similarly for all archs. When we do generic relocation, hopefully
+ * we can make all archs enable the dcache prior to relocation.
+ */
+#ifdef CONFIG_X86
+ /*
+ * SDRAM and console are now initialised. The final stack can now
+ * be setup in SDRAM. Code execution will continue in Flash, but
+ * with the stack in SDRAM and Global Data in temporary memory
+ * (CPU cache)
+ */
+ board_init_f_r_trampoline(gd->start_addr_sp);
+#elif defined(CONFIG_SANDBOX)
+ board_init_r(gd->new_gd, 0);
+#else
relocate_code(gd->dest_addr_sp, gd->new_gd, gd->dest_addr);
+#endif
return 0;
}
}
static init_fnc_t init_sequence_f[] = {
+#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC512X) && \
+ !defined(CONFIG_MPC83xx) && !defined(CONFIG_MPC85xx) && \
+ !defined(CONFIG_MPC86xx) && !defined(CONFIG_X86)
+ zero_global_data,
+#endif
+#ifdef CONFIG_SANDBOX
+ setup_ram_buf,
+#endif
setup_fdt,
setup_mon_len,
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+ /* TODO: can this go into arch_cpu_init()? */
+ probecpu,
+#endif
arch_cpu_init, /* basic arch cpu dependent setup */
+#ifdef CONFIG_X86
+ cpu_init_f, /* TODO(sjg@chromium.org): remove */
+# ifdef CONFIG_OF_CONTROL
+ find_fdt, /* TODO(sjg@chromium.org): remove */
+# endif
+#endif
mark_bootstage,
#ifdef CONFIG_OF_CONTROL
fdtdec_check_fdt,
#if defined(CONFIG_BOARD_EARLY_INIT_F)
board_early_init_f,
#endif
+ /* TODO: can any of this go into arch_cpu_init()? */
+#if defined(CONFIG_PPC) && !defined(CONFIG_8xx_CPUCLK_DEFAULT)
+ get_clocks, /* get CPU and bus clocks (etc.) */
+#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
+ && !defined(CONFIG_TQM885D)
+ adjust_sdram_tbs_8xx,
+#endif
+ /* TODO: can we rename this to timer_init()? */
+ init_timebase,
+#endif
+#ifdef CONFIG_ARM
timer_init, /* initialize timer */
+#endif
#ifdef CONFIG_BOARD_POSTCLK_INIT
board_postclk_init,
#endif
#ifdef CONFIG_FSL_ESDHC
get_clocks,
+#endif
+#ifdef CONFIG_SYS_ALLOC_DPRAM
+#if !defined(CONFIG_CPM2)
+ dpram_init,
+#endif
+#endif
+#if defined(CONFIG_BOARD_POSTCLK_INIT)
+ board_postclk_init,
#endif
env_init, /* initialize environment */
+#if defined(CONFIG_8xx_CPUCLK_DEFAULT)
+ /* get CPU and bus clocks according to the environment variable */
+ get_clocks_866,
+ /* adjust sdram refresh rate according to the new clock */
+ sdram_adjust_866,
+ init_timebase,
+#endif
init_baud_rate, /* initialze baudrate settings */
serial_init, /* serial communications setup */
console_init_f, /* stage 1 init of console */
+#ifdef CONFIG_SANDBOX
+ sandbox_early_getopt_check,
+#endif
+#ifdef CONFIG_OF_CONTROL
+ fdtdec_prepare_fdt,
+#endif
display_options, /* say that we are here */
display_text_info, /* show debugging info if required */
+#if defined(CONFIG_8260)
+ prt_8260_rsr,
+ prt_8260_clks,
+#endif /* CONFIG_8260 */
+#if defined(CONFIG_MPC83xx)
+ prt_83xx_rsr,
+#endif
+#ifdef CONFIG_PPC
+ checkcpu,
+#endif
#if defined(CONFIG_DISPLAY_CPUINFO)
print_cpuinfo, /* display cpu info (and speed) */
#endif
+#if defined(CONFIG_MPC5xxx)
+ prt_mpc5xxx_clks,
+#endif /* CONFIG_MPC5xxx */
#if defined(CONFIG_DISPLAY_BOARDINFO)
checkboard, /* display board info */
+#endif
+ INIT_FUNC_WATCHDOG_INIT
+#if defined(CONFIG_MISC_INIT_F)
+ misc_init_f,
+#endif
+ INIT_FUNC_WATCHDOG_RESET
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+ init_func_i2c,
+#endif
+#if defined(CONFIG_HARD_SPI)
+ init_func_spi,
+#endif
+#ifdef CONFIG_X86
+ dram_init_f, /* configure available RAM banks */
+ calculate_relocation_address,
#endif
announce_dram_init,
/* TODO: unify all these dram functions? */
#ifdef CONFIG_ARM
dram_init, /* configure available RAM banks */
#endif
+#ifdef CONFIG_PPC
+ init_func_ram,
+#endif
+#ifdef CONFIG_POST
+ post_init_f,
+#endif
+ INIT_FUNC_WATCHDOG_RESET
+#if defined(CONFIG_SYS_DRAM_TEST)
+ testdram,
+#endif /* CONFIG_SYS_DRAM_TEST */
+ INIT_FUNC_WATCHDOG_RESET
+
#ifdef CONFIG_POST
init_post,
#endif
+ INIT_FUNC_WATCHDOG_RESET
/*
* Now that we have DRAM mapped and working, we can
* relocate the code and continue running from DRAM.
#endif
#ifdef CONFIG_LCD
reserve_lcd,
+#endif
+ /* TODO: Why the dependency on CONFIG_8xx? */
+#if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) \
+ && !defined(CONFIG_ARM) && !defined(CONFIG_X86)
+ reserve_video,
#endif
reserve_uboot,
+#ifndef CONFIG_SPL_BUILD
reserve_malloc,
reserve_board,
+#endif
setup_machine,
reserve_global_data,
reserve_fdt,
reserve_stacks,
setup_dram_config,
show_dram_config,
+#ifdef CONFIG_PPC
+ setup_board_part1,
+ INIT_FUNC_WATCHDOG_RESET
+ setup_board_part2,
+#endif
setup_baud_rate,
display_new_sp,
+#ifdef CONFIG_SYS_EXTBDINFO
+ setup_board_extra,
+#endif
+ INIT_FUNC_WATCHDOG_RESET
reloc_fdt,
setup_reloc,
#ifndef CONFIG_ARM
void board_init_f(ulong boot_flags)
{
+#ifndef CONFIG_X86
gd_t data;
gd = &data;
+#endif
gd->flags = boot_flags;
#endif
}
-void hang(void)
+#ifdef CONFIG_X86
+/*
+ * For now this code is only used on x86.
+ *
+ * init_sequence_f_r is the list of init functions which are run when
+ * U-Boot is executing from Flash with a semi-limited 'C' environment.
+ * The following limitations must be considered when implementing an
+ * '_f_r' function:
+ * - 'static' variables are read-only
+ * - Global Data (gd->xxx) is read/write
+ *
+ * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if
+ * supported). It _should_, if possible, copy global data to RAM and
+ * initialise the CPU caches (to speed up the relocation process)
+ *
+ * NOTE: At present only x86 uses this route, but it is intended that
+ * all archs will move to this when generic relocation is implemented.
+ */
+static init_fnc_t init_sequence_f_r[] = {
+ init_cache_f_r,
+ copy_uboot_to_ram,
+ clear_bss,
+ do_elf_reloc_fixups,
+
+ NULL,
+};
+
+void board_init_f_r(void)
{
- puts("### ERROR ### Please RESET the board ###\n");
- for (;;);
+ if (initcall_run_list(init_sequence_f_r))
+ hang();
+
+ /*
+ * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
+ * Transfer execution from Flash to RAM by calculating the address
+ * of the in-RAM copy of board_init_r() and calling it
+ */
+ (board_init_r + gd->reloc_off)(gd, gd->relocaddr);
+
+ /* NOTREACHED - board_init_r() does not return */
+ hang();
}
+#endif /* CONFIG_X86 */
projects / karo-tx-uboot.git / blobdiff