imported Freescale specific U-Boot additions for i.MX28,... release L2.6.31_10.08.01

[karo-tx-uboot.git] / cpu / 74xx_7xx / kgdb.S

diff --git a/cpu/74xx_7xx/kgdb.S b/cpu/74xx_7xx/kgdb.S
index e838513c1df1e159e353140db56398e88bb59a25..ad487cdaf45007b03944d2136774a70b989ab03d 100755 (executable)
--- a/cpu/74xx_7xx/kgdb.S
+++ b/cpu/74xx_7xx/kgdb.S
@@ -31,7 +31,7 @@
 #include <asm/cache.h>
 #include <asm/mmu.h>
 
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 
  /*
  * cache flushing routines for kgdb
@@ -43,7 +43,7 @@ kgdb_flush_cache_all:
        addis   r4,r0,0x0040
 kgdb_flush_loop:
        lwz     r5,0(r3)
-       addi    r3,r3,CFG_CACHELINE_SIZE
+       addi    r3,r3,CONFIG_SYS_CACHELINE_SIZE
        cmp     0,0,r3,r4
        bne     kgdb_flush_loop
        SYNC
@@ -55,23 +55,23 @@ kgdb_flush_loop:
 
        .globl  kgdb_flush_cache_range
 kgdb_flush_cache_range:
-       li      r5,CFG_CACHELINE_SIZE-1
+       li      r5,CONFIG_SYS_CACHELINE_SIZE-1
        andc    r3,r3,r5
        subf    r4,r3,r4
        add     r4,r4,r5
-       srwi.   r4,r4,CFG_CACHELINE_SHIFT
+       srwi.   r4,r4,CONFIG_SYS_CACHELINE_SHIFT
        beqlr
        mtctr   r4
        mr      r6,r3
 1:     dcbst   0,r3
-       addi    r3,r3,CFG_CACHELINE_SIZE
+       addi    r3,r3,CONFIG_SYS_CACHELINE_SIZE
        bdnz    1b
        sync                            /* wait for dcbst's to get to ram */
        mtctr   r4
 2:     icbi    0,r6
-       addi    r6,r6,CFG_CACHELINE_SIZE
+       addi    r6,r6,CONFIG_SYS_CACHELINE_SIZE
        bdnz    2b
        SYNC
        blr
 
-#endif /* CFG_CMD_KGDB */
+#endif