arm: clean cache management

[karo-tx-uboot.git] / cpu / arm925t / cpu.c

diff --git a/cpu/arm925t/cpu.c b/cpu/arm925t/cpu.c
index b9f09318ad52cb2189b46db763a527052bef0f73..eb6364d6945cce724bbef4cd8ecd23e30ec5cbac 100644 (file)
--- a/cpu/arm925t/cpu.c
+++ b/cpu/arm925t/cpu.c
@@ -32,62 +32,13 @@
 #include <common.h>
 #include <command.h>
 #include <arm925t.h>
+#include <asm/system.h>
 
 #ifdef CONFIG_USE_IRQ
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
-/* read co-processor 15, register #1 (control register) */
-static unsigned long read_p15_c1 (void)
-{
-       unsigned long value;
-
-       __asm__ __volatile__(
-               "mrc    p15, 0, %0, c1, c0, 0   @ read control reg\n"
-               : "=r" (value)
-               :
-               : "memory");
-
-#ifdef MMU_DEBUG
-       printf ("p15/c1 is = %08lx\n", value);
-#endif
-       return value;
-}
-
-/* write to co-processor 15, register #1 (control register) */
-static void write_p15_c1 (unsigned long value)
-{
-#ifdef MMU_DEBUG
-       printf ("write %08lx to p15/c1\n", value);
-#endif
-       __asm__ __volatile__(
-               "mcr    p15, 0, %0, c1, c0, 0   @ write it back\n"
-               :
-               : "r" (value)
-               : "memory");
-
-       read_p15_c1 ();
-}
-
-static void cp_delay (void)
-{
-       volatile int i;
-
-       /* Many OMAP regs need at least 2 nops  */
-       for (i = 0; i < 100; i++);
-}
-
-/* See also ARM Ref. Man. */
-#define C1_MMU         (1<<0)          /* mmu off/on */
-#define C1_ALIGN       (1<<1)          /* alignment faults off/on */
-#define C1_DC          (1<<2)          /* dcache off/on */
-#define C1_WB          (1<<3)          /* merging write buffer on/off */
-#define C1_BIG_ENDIAN  (1<<7)  /* big endian off/on */
-#define C1_SYS_PROT    (1<<8)          /* system protection */
-#define C1_ROM_PROT    (1<<9)          /* ROM protection */
-#define C1_IC          (1<<12)         /* icache off/on */
-#define C1_HIGH_VECTORS        (1<<13) /* location of vectors: low/high addresses */
-#define RESERVED_1     (0xf << 3)      /* must be 111b for R/W */
+static void cache_flush(void);
 
 int cpu_init (void)
 {
@@ -110,19 +61,16 @@ int cleanup_before_linux (void)
         * we turn off caches etc ...
         */
 
-       unsigned long i;
-
        disable_interrupts ();
 
-       /* turn off I/D-cache */
-       asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-       i &= ~(C1_DC | C1_IC);
-       asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 
+       /* turn off I/D-cache */
+       icache_disable();
+       dcache_disable();
        /* flush I/D-cache */
-       i = 0;
-       asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
-       return (0);
+       cache_flush();
+
+       return 0;
 }
 
 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
@@ -133,25 +81,11 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
        return (0);
 }
 
-void icache_enable (void)
+/* flush I/D-cache */
+static void cache_flush (void)
 {
-       ulong reg;
+       unsigned long i = 0;
 
-       reg = read_p15_c1 ();           /* get control reg. */
-       cp_delay ();
-       write_p15_c1 (reg | C1_IC);
-}
-
-void icache_disable (void)
-{
-       ulong reg;
-
-       reg = read_p15_c1 ();
-       cp_delay ();
-       write_p15_c1 (reg & ~C1_IC);
+       asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
 }
 
-int icache_status (void)
-{
-       return (read_p15_c1 () & C1_IC) != 0;
-}