ppc: Refactor cache routines, so there is only one common set.

[karo-tx-uboot.git] / cpu / mpc512x / start.S

diff --git a/cpu/mpc512x/start.S b/cpu/mpc512x/start.S
index 244c69b8124f0dcbbab3784224f93a2f810607c8..5a9d8687f5b6c538954a63b77fc4ae1f6035931f 100644 (file)
--- a/cpu/mpc512x/start.S
+++ b/cpu/mpc512x/start.S
@@ -479,52 +479,6 @@ get_pvr:
        mfspr   r3, PVR
        blr
 
-/*------------------------------------------------------------------------------- */
-/* Function:    ppcDcbf */
-/* Description:         Data Cache block flush */
-/* Input:       r3 = effective address */
-/* Output:      none. */
-/*------------------------------------------------------------------------------- */
-       .globl  ppcDcbf
-ppcDcbf:
-       dcbf    r0,r3
-       blr
-
-/*------------------------------------------------------------------------------- */
-/* Function:    ppcDcbi */
-/* Description:         Data Cache block Invalidate */
-/* Input:       r3 = effective address */
-/* Output:      none. */
-/*------------------------------------------------------------------------------- */
-       .globl  ppcDcbi
-ppcDcbi:
-       dcbi    r0,r3
-       blr
-
-/*--------------------------------------------------------------------------
- * Function:    ppcDcbz
- * Description:         Data Cache block zero.
- * Input:       r3 = effective address
- * Output:      none.
- *-------------------------------------------------------------------------- */
-
-       .globl  ppcDcbz
-ppcDcbz:
-       dcbz    r0,r3
-       blr
-
-       .globl  ppcDWstore
-ppcDWstore:
-       lfd     1, 0(r4)
-       stfd    1, 0(r3)
-       blr
-
-       .globl  ppcDWload
-ppcDWload:
-       lfd     1, 0(r3)
-       stfd    1, 0(r4)
-       blr
-
 /*-------------------------------------------------------------------*/
 
 /*