imported Ka-Ro specific additions to U-Boot 2009.08 for TX28

[karo-tx-uboot.git] / cpu / mpc86xx / cache.S

diff --git a/cpu/mpc86xx/cache.S b/cpu/mpc86xx/cache.S
index f316b3ec13fe59ea4012714d58617b82e12f7d66..0bb058b043f30a8183397a03053bb79efbf49503 100755 (executable)
--- a/cpu/mpc86xx/cache.S
+++ b/cpu/mpc86xx/cache.S
@@ -53,7 +53,7 @@ _GLOBAL(invalidate_l1_data_cache)
 /*
  * Flush data cache.
  */
-_GLOBAL(flush_data_cache)
+_GLOBAL(flush_dcache)
        lis     r3,0
        lis     r5,CACHE_LINE_SIZE
 flush:
@@ -232,6 +232,10 @@ _GLOBAL(icache_enable)
  * Disable L1 Instruction cache
  */
 _GLOBAL(icache_disable)
+       mflr    r4
+       bl      invalidate_l1_instruction_cache         /* uses r3 */
+       sync
+       mtlr    r4
        mfspr   r3, HID0
        li      r5, 0
        ori     r5, r5, HID0_ICE
@@ -275,7 +279,7 @@ _GLOBAL(dcache_enable)
        mtspr   HID0, r5                /* enable + invalidate */
        mtspr   HID0, r3                /* enable */
        sync
-#ifdef CFG_L2
+#ifdef CONFIG_SYS_L2
        mflr    r5
        bl      l2cache_enable          /* uses r3 and r4 */
        sync
@@ -286,12 +290,12 @@ _GLOBAL(dcache_enable)
 
 /*
  * Disable data cache(s) - L1 and optionally L2
- * Calls flush_data_cache and l2cache_disable_no_flush.
+ * Calls flush_dcache and l2cache_disable_no_flush.
  * LR saved in r4
  */
 _GLOBAL(dcache_disable)
        mflr    r4                      /* save link register */
-       bl      flush_data_cache        /* uses r3 and r5 */
+       bl      flush_dcache    /* uses r3 and r5 */
        sync
        mfspr   r3, HID0
        li      r5, HID0_DCFI|HID0_DLOCK
@@ -301,7 +305,7 @@ _GLOBAL(dcache_disable)
        andc    r3, r3, r5              /* no enable, no invalidate */
        mtspr   HID0, r3
        sync
-#ifdef CFG_L2
+#ifdef CONFIG_SYS_L2
        bl      l2cache_disable_no_flush /* uses r3 */
 #endif
        mtlr    r4                      /* restore link register */
@@ -338,7 +342,7 @@ _GLOBAL(l2cache_invalidate)
 
 invl2:
        mfspr   r3, l2cr
-       andi.   r3, r3, L2CR_L2I@h
+       andis.  r3, r3, L2CR_L2I@h
        bne     invl2
        blr
 
@@ -359,11 +363,11 @@ _GLOBAL(l2cache_enable)
 
 /*
  * Disable L2 cache
- * Calls flush_data_cache. LR is saved in r4
+ * Calls flush_dcache. LR is saved in r4
  */
 _GLOBAL(l2cache_disable)
        mflr    r4                      /* save link register */
-       bl      flush_data_cache        /* uses r3 and r5 */
+       bl      flush_dcache            /* uses r3 and r5 */
        sync
        mtlr    r4                      /* restore link register */
 l2cache_disable_no_flush:              /* provide way to disable L2 w/o flushing */