"SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
} while (0)
-static void ppc4xx_ibm_ddr2_register_dump(void);
-
#if defined(CONFIG_SPD_EEPROM)
/*-----------------------------------------------------------------------------+
#define ODS_FULL 0x00000000
#define ODS_REDUCED 0x00000002
+#define OCD_CALIB_DEF 0x00000380
/* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
#define ODT_EB0R (0x80000000 >> 8)
unsigned long num_bytes,
unsigned long tlb_word2_i_value);
#endif
+#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
static void program_DQS_calibration(unsigned long *dimm_populated,
- unsigned char *iic0_dimm_addr,
- unsigned long num_dimm_banks);
+ unsigned char *iic0_dimm_addr,
+ unsigned long num_dimm_banks);
#ifdef HARD_CODED_DQS /* calibration test with hardvalues */
static void test(void);
#else
static void DQS_calibration_process(void);
#endif
+#endif
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
void dcbz_area(u32 start_address, u32 num_bytes);
-static u32 mfdcr_any(u32 dcr)
-{
- u32 val;
-
- switch (dcr) {
- case SDRAM_R0BAS + 0:
- val = mfdcr(SDRAM_R0BAS + 0);
- break;
- case SDRAM_R0BAS + 1:
- val = mfdcr(SDRAM_R0BAS + 1);
- break;
- case SDRAM_R0BAS + 2:
- val = mfdcr(SDRAM_R0BAS + 2);
- break;
- case SDRAM_R0BAS + 3:
- val = mfdcr(SDRAM_R0BAS + 3);
- break;
- default:
- printf("DCR %d not defined in case statement!!!\n", dcr);
- val = 0; /* just to satisfy the compiler */
- }
-
- return val;
-}
-
-static void mtdcr_any(u32 dcr, u32 val)
-{
- switch (dcr) {
- case SDRAM_R0BAS + 0:
- mtdcr(SDRAM_R0BAS + 0, val);
- break;
- case SDRAM_R0BAS + 1:
- mtdcr(SDRAM_R0BAS + 1, val);
- break;
- case SDRAM_R0BAS + 2:
- mtdcr(SDRAM_R0BAS + 2, val);
- break;
- case SDRAM_R0BAS + 3:
- mtdcr(SDRAM_R0BAS + 3, val);
- break;
- default:
- printf("DCR %d not defined in case statement!!!\n", dcr);
- }
-}
-
static unsigned char spd_read(uchar chip, uint addr)
{
unsigned char data[2];
*/
/* switch to correct I2C bus */
- I2C_SET_BUS(CFG_SPD_BUS_NUM);
- i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
/*------------------------------------------------------------------
* Clear out the serial presence detect buffers.
mtsdram(SDRAM_MCOPT2,
(val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
- (SDRAM_MCOPT2_DCEN_ENABLE | SDRAM_MCOPT2_IPTR_EXECUTE));
+ SDRAM_MCOPT2_IPTR_EXECUTE);
/*------------------------------------------------------------------
- * Wait for SDRAM_CFG0_DC_EN to complete.
+ * Wait for IPTR_EXECUTE init sequence to complete.
*-----------------------------------------------------------------*/
do {
mfsdram(SDRAM_MCSTAT, val);
} while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
+ /* enable the controller only after init sequence completes */
+ mfsdram(SDRAM_MCOPT2, val);
+ mtsdram(SDRAM_MCOPT2, (val | SDRAM_MCOPT2_DCEN_ENABLE));
+
+ /* Make sure delay-line calibration is done before proceeding */
+ do {
+ mfsdram(SDRAM_DLCR, val);
+ } while (!(val & SDRAM_DLCR_DLCS_COMPLETE));
+
/* get installed memory size */
dram_size = sdram_memsize();
/*------------------------------------------------------------------
* DQS calibration.
*-----------------------------------------------------------------*/
+#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
+ DQS_autocalibration();
+#else
program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
+#endif
#ifdef CONFIG_DDR_ECC
/*------------------------------------------------------------------
if (dimm_type == SDRAM_DDR2) {
codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
if ((total_dimm == 1) && (firstSlot == TRUE)) {
- if (total_rank == 1) {
+ if (total_rank == 1) { /* PUUU */
codt |= CALC_ODT_R(0);
modt0 = CALC_ODT_W(0);
modt1 = 0x00000000;
modt2 = 0x00000000;
modt3 = 0x00000000;
}
- if (total_rank == 2) {
+ if (total_rank == 2) { /* PPUU */
codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
- modt0 = CALC_ODT_W(0);
- modt1 = CALC_ODT_W(0);
+ modt0 = CALC_ODT_W(0) | CALC_ODT_W(1);
+ modt1 = 0x00000000;
modt2 = 0x00000000;
modt3 = 0x00000000;
}
} else if ((total_dimm == 1) && (firstSlot != TRUE)) {
- if (total_rank == 1) {
+ if (total_rank == 1) { /* UUPU */
codt |= CALC_ODT_R(2);
modt0 = 0x00000000;
modt1 = 0x00000000;
modt2 = CALC_ODT_W(2);
modt3 = 0x00000000;
}
- if (total_rank == 2) {
+ if (total_rank == 2) { /* UUPP */
codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
modt0 = 0x00000000;
modt1 = 0x00000000;
- modt2 = CALC_ODT_W(2);
- modt3 = CALC_ODT_W(2);
+ modt2 = CALC_ODT_W(2) | CALC_ODT_W(3);
+ modt3 = 0x00000000;
}
}
if (total_dimm == 2) {
- if (total_rank == 2) {
+ if (total_rank == 2) { /* PUPU */
codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
modt0 = CALC_ODT_RW(2);
modt1 = 0x00000000;
modt2 = CALC_ODT_RW(0);
modt3 = 0x00000000;
}
- if (total_rank == 4) {
+ if (total_rank == 4) { /* PPPP */
codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
CALC_ODT_R(2) | CALC_ODT_R(3);
- modt0 = CALC_ODT_RW(2);
+ modt0 = CALC_ODT_RW(2) | CALC_ODT_RW(3);
modt1 = 0x00000000;
- modt2 = CALC_ODT_RW(0);
+ modt2 = CALC_ODT_RW(0) | CALC_ODT_RW(1);
modt3 = 0x00000000;
}
}
emr = CMD_EMR | SELECT_EMR | odt | ods;
emr2 = CMD_EMR | SELECT_EMR2;
emr3 = CMD_EMR | SELECT_EMR3;
- mtsdram(SDRAM_INITPLR0, 0xB5000000 | CMD_NOP); /* NOP */
+ /* NOP - Wait 106 MemClk cycles */
+ mtsdram(SDRAM_INITPLR0, SDRAM_INITPLR_ENABLE | CMD_NOP |
+ SDRAM_INITPLR_IMWT_ENCODE(106));
udelay(1000);
- mtsdram(SDRAM_INITPLR1, 0x82000400 | CMD_PRECHARGE); /* precharge 8 DDR clock cycle */
- mtsdram(SDRAM_INITPLR2, 0x80800000 | emr2); /* EMR2 */
- mtsdram(SDRAM_INITPLR3, 0x80800000 | emr3); /* EMR3 */
- mtsdram(SDRAM_INITPLR4, 0x80800000 | emr); /* EMR DLL ENABLE */
- mtsdram(SDRAM_INITPLR5, 0x80800000 | mr | DLL_RESET); /* MR w/ DLL reset */
+ /* precharge 4 MemClk cycles */
+ mtsdram(SDRAM_INITPLR1, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
+ SDRAM_INITPLR_IMWT_ENCODE(4));
+ /* EMR2 - Wait tMRD (2 MemClk cycles) */
+ mtsdram(SDRAM_INITPLR2, SDRAM_INITPLR_ENABLE | emr2 |
+ SDRAM_INITPLR_IMWT_ENCODE(2));
+ /* EMR3 - Wait tMRD (2 MemClk cycles) */
+ mtsdram(SDRAM_INITPLR3, SDRAM_INITPLR_ENABLE | emr3 |
+ SDRAM_INITPLR_IMWT_ENCODE(2));
+ /* EMR DLL ENABLE - Wait tMRD (2 MemClk cycles) */
+ mtsdram(SDRAM_INITPLR4, SDRAM_INITPLR_ENABLE | emr |
+ SDRAM_INITPLR_IMWT_ENCODE(2));
+ /* MR w/ DLL reset - 200 cycle wait for DLL reset */
+ mtsdram(SDRAM_INITPLR5, SDRAM_INITPLR_ENABLE | mr | DLL_RESET |
+ SDRAM_INITPLR_IMWT_ENCODE(200));
udelay(1000);
- mtsdram(SDRAM_INITPLR6, 0x82000400 | CMD_PRECHARGE); /* precharge 8 DDR clock cycle */
- mtsdram(SDRAM_INITPLR7, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
- mtsdram(SDRAM_INITPLR8, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
- mtsdram(SDRAM_INITPLR9, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
- mtsdram(SDRAM_INITPLR10, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
- mtsdram(SDRAM_INITPLR11, 0x80000000 | mr); /* MR w/o DLL reset */
- mtsdram(SDRAM_INITPLR12, 0x80800380 | emr); /* EMR OCD Default */
- mtsdram(SDRAM_INITPLR13, 0x80800000 | emr); /* EMR OCD Exit */
+ /* precharge 4 MemClk cycles */
+ mtsdram(SDRAM_INITPLR6, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
+ SDRAM_INITPLR_IMWT_ENCODE(4));
+ /* Refresh 25 MemClk cycles */
+ mtsdram(SDRAM_INITPLR7, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
+ SDRAM_INITPLR_IMWT_ENCODE(25));
+ /* Refresh 25 MemClk cycles */
+ mtsdram(SDRAM_INITPLR8, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
+ SDRAM_INITPLR_IMWT_ENCODE(25));
+ /* Refresh 25 MemClk cycles */
+ mtsdram(SDRAM_INITPLR9, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
+ SDRAM_INITPLR_IMWT_ENCODE(25));
+ /* Refresh 25 MemClk cycles */
+ mtsdram(SDRAM_INITPLR10, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
+ SDRAM_INITPLR_IMWT_ENCODE(25));
+ /* MR w/o DLL reset - Wait tMRD (2 MemClk cycles) */
+ mtsdram(SDRAM_INITPLR11, SDRAM_INITPLR_ENABLE | mr |
+ SDRAM_INITPLR_IMWT_ENCODE(2));
+ /* EMR OCD Default - Wait tMRD (2 MemClk cycles) */
+ mtsdram(SDRAM_INITPLR12, SDRAM_INITPLR_ENABLE | OCD_CALIB_DEF |
+ SDRAM_INITPLR_IMWT_ENCODE(2) | emr);
+ /* EMR OCD Exit */
+ mtsdram(SDRAM_INITPLR13, SDRAM_INITPLR_ENABLE | emr |
+ SDRAM_INITPLR_IMWT_ENCODE(2));
} else {
printf("ERROR: ucode error as unknown DDR type in program_initplr");
spd_ddr_init_hang ();
}
}
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+ defined(CONFIG_460SX)
/*
- * Enable high bandwidth access on 460EX/GT.
- * This should/could probably be done on other
- * PPC's too, like 440SPe.
+ * Enable high bandwidth access
* This is currently not used, but with this setup
* it is possible to use it later on in e.g. the Linux
* EMAC driver for performance gain.
*/
mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
+
+ /*
+ * Set optimal value for Memory Queue HB/LL Configuration registers
+ */
+ mtdcr(SDRAM_CONF1HB, mfdcr(SDRAM_CONF1HB) | SDRAM_CONF1HB_AAFR |
+ SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE);
+ mtdcr(SDRAM_CONF1LL, mfdcr(SDRAM_CONF1LL) | SDRAM_CONF1LL_AAFR |
+ SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE);
+ mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
#endif
}
return ecc;
}
-static void blank_string(int size)
-{
- int i;
-
- for (i=0; i<size; i++)
- putc('\b');
- for (i=0; i<size; i++)
- putc(' ');
- for (i=0; i<size; i++)
- putc('\b');
-}
-
#ifdef CONFIG_DDR_ECC
/*-----------------------------------------------------------------------------+
* program_ecc.
}
#endif
+#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
/*-----------------------------------------------------------------------------+
* program_DQS_calibration.
*-----------------------------------------------------------------------------*/
* Program RFDC register
* Set Feedback Fractional Oversample
* Auto-detect read sample cycle enable
+ * Set RFOS to 1/4 of memclk cycle (0x3f)
*-----------------------------------------------------------------*/
mfsdram(SDRAM_RFDC, val);
mtsdram(SDRAM_RFDC,
(val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
SDRAM_RFDC_RFFD_MASK))
- | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0) |
+ | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0x3f) |
SDRAM_RFDC_RFFD_ENCODE(0)));
DQS_calibration_process();
(ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
| ecc_temp);
}
-#endif
+#endif /* !HARD_CODED_DQS */
+#endif /* !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */
#else /* CONFIG_SPD_EEPROM */
/* Set Memory Bank Configuration Registers */
- mtsdram(SDRAM_MB0CF, CFG_SDRAM0_MB0CF);
- mtsdram(SDRAM_MB1CF, CFG_SDRAM0_MB1CF);
- mtsdram(SDRAM_MB2CF, CFG_SDRAM0_MB2CF);
- mtsdram(SDRAM_MB3CF, CFG_SDRAM0_MB3CF);
+ mtsdram(SDRAM_MB0CF, CONFIG_SYS_SDRAM0_MB0CF);
+ mtsdram(SDRAM_MB1CF, CONFIG_SYS_SDRAM0_MB1CF);
+ mtsdram(SDRAM_MB2CF, CONFIG_SYS_SDRAM0_MB2CF);
+ mtsdram(SDRAM_MB3CF, CONFIG_SYS_SDRAM0_MB3CF);
/* Set Memory Clock Timing Register */
- mtsdram(SDRAM_CLKTR, CFG_SDRAM0_CLKTR);
+ mtsdram(SDRAM_CLKTR, CONFIG_SYS_SDRAM0_CLKTR);
/* Set Refresh Time Register */
- mtsdram(SDRAM_RTR, CFG_SDRAM0_RTR);
+ mtsdram(SDRAM_RTR, CONFIG_SYS_SDRAM0_RTR);
/* Set SDRAM Timing Registers */
- mtsdram(SDRAM_SDTR1, CFG_SDRAM0_SDTR1);
- mtsdram(SDRAM_SDTR2, CFG_SDRAM0_SDTR2);
- mtsdram(SDRAM_SDTR3, CFG_SDRAM0_SDTR3);
+ mtsdram(SDRAM_SDTR1, CONFIG_SYS_SDRAM0_SDTR1);
+ mtsdram(SDRAM_SDTR2, CONFIG_SYS_SDRAM0_SDTR2);
+ mtsdram(SDRAM_SDTR3, CONFIG_SYS_SDRAM0_SDTR3);
/* Set Mode and Extended Mode Registers */
- mtsdram(SDRAM_MMODE, CFG_SDRAM0_MMODE);
- mtsdram(SDRAM_MEMODE, CFG_SDRAM0_MEMODE);
+ mtsdram(SDRAM_MMODE, CONFIG_SYS_SDRAM0_MMODE);
+ mtsdram(SDRAM_MEMODE, CONFIG_SYS_SDRAM0_MEMODE);
/* Set Memory Controller Options 1 Register */
- mtsdram(SDRAM_MCOPT1, CFG_SDRAM0_MCOPT1);
+ mtsdram(SDRAM_MCOPT1, CONFIG_SYS_SDRAM0_MCOPT1);
/* Set Manual Initialization Control Registers */
- mtsdram(SDRAM_INITPLR0, CFG_SDRAM0_INITPLR0);
- mtsdram(SDRAM_INITPLR1, CFG_SDRAM0_INITPLR1);
- mtsdram(SDRAM_INITPLR2, CFG_SDRAM0_INITPLR2);
- mtsdram(SDRAM_INITPLR3, CFG_SDRAM0_INITPLR3);
- mtsdram(SDRAM_INITPLR4, CFG_SDRAM0_INITPLR4);
- mtsdram(SDRAM_INITPLR5, CFG_SDRAM0_INITPLR5);
- mtsdram(SDRAM_INITPLR6, CFG_SDRAM0_INITPLR6);
- mtsdram(SDRAM_INITPLR7, CFG_SDRAM0_INITPLR7);
- mtsdram(SDRAM_INITPLR8, CFG_SDRAM0_INITPLR8);
- mtsdram(SDRAM_INITPLR9, CFG_SDRAM0_INITPLR9);
- mtsdram(SDRAM_INITPLR10, CFG_SDRAM0_INITPLR10);
- mtsdram(SDRAM_INITPLR11, CFG_SDRAM0_INITPLR11);
- mtsdram(SDRAM_INITPLR12, CFG_SDRAM0_INITPLR12);
- mtsdram(SDRAM_INITPLR13, CFG_SDRAM0_INITPLR13);
- mtsdram(SDRAM_INITPLR14, CFG_SDRAM0_INITPLR14);
- mtsdram(SDRAM_INITPLR15, CFG_SDRAM0_INITPLR15);
+ mtsdram(SDRAM_INITPLR0, CONFIG_SYS_SDRAM0_INITPLR0);
+ mtsdram(SDRAM_INITPLR1, CONFIG_SYS_SDRAM0_INITPLR1);
+ mtsdram(SDRAM_INITPLR2, CONFIG_SYS_SDRAM0_INITPLR2);
+ mtsdram(SDRAM_INITPLR3, CONFIG_SYS_SDRAM0_INITPLR3);
+ mtsdram(SDRAM_INITPLR4, CONFIG_SYS_SDRAM0_INITPLR4);
+ mtsdram(SDRAM_INITPLR5, CONFIG_SYS_SDRAM0_INITPLR5);
+ mtsdram(SDRAM_INITPLR6, CONFIG_SYS_SDRAM0_INITPLR6);
+ mtsdram(SDRAM_INITPLR7, CONFIG_SYS_SDRAM0_INITPLR7);
+ mtsdram(SDRAM_INITPLR8, CONFIG_SYS_SDRAM0_INITPLR8);
+ mtsdram(SDRAM_INITPLR9, CONFIG_SYS_SDRAM0_INITPLR9);
+ mtsdram(SDRAM_INITPLR10, CONFIG_SYS_SDRAM0_INITPLR10);
+ mtsdram(SDRAM_INITPLR11, CONFIG_SYS_SDRAM0_INITPLR11);
+ mtsdram(SDRAM_INITPLR12, CONFIG_SYS_SDRAM0_INITPLR12);
+ mtsdram(SDRAM_INITPLR13, CONFIG_SYS_SDRAM0_INITPLR13);
+ mtsdram(SDRAM_INITPLR14, CONFIG_SYS_SDRAM0_INITPLR14);
+ mtsdram(SDRAM_INITPLR15, CONFIG_SYS_SDRAM0_INITPLR15);
/* Set On-Die Termination Registers */
- mtsdram(SDRAM_CODT, CFG_SDRAM0_CODT);
- mtsdram(SDRAM_MODT0, CFG_SDRAM0_MODT0);
- mtsdram(SDRAM_MODT1, CFG_SDRAM0_MODT1);
+ mtsdram(SDRAM_CODT, CONFIG_SYS_SDRAM0_CODT);
+ mtsdram(SDRAM_MODT0, CONFIG_SYS_SDRAM0_MODT0);
+ mtsdram(SDRAM_MODT1, CONFIG_SYS_SDRAM0_MODT1);
/* Set Write Timing Register */
- mtsdram(SDRAM_WRDTR, CFG_SDRAM0_WRDTR);
+ mtsdram(SDRAM_WRDTR, CONFIG_SYS_SDRAM0_WRDTR);
/*
* Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
/* Set Delay Control Registers */
- mtsdram(SDRAM_DLCR, CFG_SDRAM0_DLCR);
- mtsdram(SDRAM_RDCC, CFG_SDRAM0_RDCC);
- mtsdram(SDRAM_RQDC, CFG_SDRAM0_RQDC);
- mtsdram(SDRAM_RFDC, CFG_SDRAM0_RFDC);
+ mtsdram(SDRAM_DLCR, CONFIG_SYS_SDRAM0_DLCR);
+
+#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
+ mtsdram(SDRAM_RDCC, CONFIG_SYS_SDRAM0_RDCC);
+ mtsdram(SDRAM_RQDC, CONFIG_SYS_SDRAM0_RQDC);
+ mtsdram(SDRAM_RFDC, CONFIG_SYS_SDRAM0_RFDC);
+#endif /* !CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
/*
* Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
mfsdram(SDRAM_MCOPT2, val);
mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
+#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+ /*------------------------------------------------------------------
+ | DQS calibration.
+ +-----------------------------------------------------------------*/
+ DQS_autocalibration();
+#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
+#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
+
#if defined(CONFIG_DDR_ECC)
- ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
+ ecc_init(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20);
#endif /* defined(CONFIG_DDR_ECC) */
ppc4xx_ibm_ddr2_register_dump();
+
+#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
+ /*
+ * Clear potential errors resulting from auto-calibration.
+ * If not done, then we could get an interrupt later on when
+ * exceptions are enabled.
+ */
+ set_mcsr(get_mcsr());
+#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
+
#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
- return (CFG_MBYTES_SDRAM << 20);
+ return (CONFIG_SYS_MBYTES_SDRAM << 20);
}
#endif /* CONFIG_SPD_EEPROM */
-static void ppc4xx_ibm_ddr2_register_dump(void)
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_440)
+u32 mfdcr_any(u32 dcr)
+{
+ u32 val;
+
+ switch (dcr) {
+ case SDRAM_R0BAS + 0:
+ val = mfdcr(SDRAM_R0BAS + 0);
+ break;
+ case SDRAM_R0BAS + 1:
+ val = mfdcr(SDRAM_R0BAS + 1);
+ break;
+ case SDRAM_R0BAS + 2:
+ val = mfdcr(SDRAM_R0BAS + 2);
+ break;
+ case SDRAM_R0BAS + 3:
+ val = mfdcr(SDRAM_R0BAS + 3);
+ break;
+ default:
+ printf("DCR %d not defined in case statement!!!\n", dcr);
+ val = 0; /* just to satisfy the compiler */
+ }
+
+ return val;
+}
+
+void mtdcr_any(u32 dcr, u32 val)
+{
+ switch (dcr) {
+ case SDRAM_R0BAS + 0:
+ mtdcr(SDRAM_R0BAS + 0, val);
+ break;
+ case SDRAM_R0BAS + 1:
+ mtdcr(SDRAM_R0BAS + 1, val);
+ break;
+ case SDRAM_R0BAS + 2:
+ mtdcr(SDRAM_R0BAS + 2, val);
+ break;
+ case SDRAM_R0BAS + 3:
+ mtdcr(SDRAM_R0BAS + 3, val);
+ break;
+ default:
+ printf("DCR %d not defined in case statement!!!\n", dcr);
+ }
+}
+#endif /* defined(CONFIG_440) */
+
+void blank_string(int size)
+{
+ int i;
+
+ for (i = 0; i < size; i++)
+ putc('\b');
+ for (i = 0; i < size; i++)
+ putc(' ');
+ for (i = 0; i < size; i++)
+ putc('\b');
+}
+#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
+
+inline void ppc4xx_ibm_ddr2_register_dump(void)
{
#if defined(DEBUG)
printf("\nPPC4xx IBM DDR2 Register Dump:\n");
projects / karo-tx-uboot.git / blobdiff