rename CFG_ macros to CONFIG_SYS

[karo-tx-uboot.git] / cpu / ppc4xx / denali_spd_ddr2.c

diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c
index 60f89c97fc804fdb2e03ff4f320b0bd3b8a9c47e..4705e21b57c0b01d64f337d688656fd52fc3420c 100644 (file)
--- a/cpu/ppc4xx/denali_spd_ddr2.c
+++ b/cpu/ppc4xx/denali_spd_ddr2.c
@@ -45,6 +45,7 @@
 #include <asm/io.h>
 #include <asm/processor.h>
 #include <asm/mmu.h>
+#include <asm/cache.h>
 
 #if defined(CONFIG_SPD_EEPROM) &&                              \
        (defined(CONFIG_440EPX) || defined(CONFIG_440GRX))
@@ -92,7 +93,6 @@
 extern int denali_wait_for_dlllock(void);
 extern void denali_core_search_data_eye(void);
 extern void dcbz_area(u32 start_address, u32 num_bytes);
-extern void dflush(void);
 
 /*
  * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
@@ -339,7 +339,7 @@ static void get_spd_info(unsigned long dimm_ranks[],
                              "\n", dimm_num, ranks_on_dimm);
                        if (ranks_on_dimm > max_ranks_per_dimm) {
                                printf("WARNING: DRAM DIMM in slot %lu has %lu "
-                                      "ranks.\n");
+                                      "ranks.\n", dimm_num, ranks_on_dimm);
                                if (1 == max_ranks_per_dimm) {
                                        printf("Only one rank will be used.\n");
                                } else {
@@ -668,8 +668,8 @@ static void program_ddr0_03(unsigned long dimm_ranks[],
                       "and 5.0 are supported.\n");
                printf("Make sure the PLB speed is within the supported range "
                       "of the DIMMs.\n");
-               printf("sdram_freq=%d cycle2=%d cycle3=%d cycle4=%d "
-                      "cycle5=%d\n\n", sdram_freq, cycle_2_0_clk,
+               printf("sdram_freq=%ld cycle2=%ld cycle3=%ld cycle4=%ld "
+                      "cycle5=%ld\n\n", sdram_freq, cycle_2_0_clk,
                       cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
                spd_ddr_init_hang();
        }
@@ -1022,7 +1022,7 @@ static void program_ddr0_44(unsigned long dimm_ranks[],
  *              banks appropriately. If Auto Memory Configuration is
  *              not used, it is assumed that no DIMM is plugged
  *-----------------------------------------------------------------------------*/
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
 {
        unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
        unsigned long dimm_ranks[MAXDIMMS];
@@ -1048,8 +1048,8 @@ long int initdram(int board_type)
         * before continuing.
         */
        /* switch to correct I2C bus */
-       I2C_SET_BUS(CFG_SPD_BUS_NUM);
-       i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+       I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
+       i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
        /*------------------------------------------------------------------
         * Clear out the serial presence detect buffers.
@@ -1093,10 +1093,10 @@ long int initdram(int board_type)
 
        program_ddr0_06(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
 
-       /*------------------------------------------------------------------
+       /*
         * TODO: tFAW not found in SPD.  Value of 13 taken from Sequoia
-        * board SDRAM, but may be overly concervate.
-        *-----------------------------------------------------------------*/
+        * board SDRAM, but may be overly conservative.
+        */
        mtsdram(DDR0_07, DDR0_07_NO_CMD_INIT_ENCODE(0) |
                DDR0_07_TFAW_ENCODE(13) |
                DDR0_07_AUTO_REFRESH_MODE_ENCODE(1) |
@@ -1181,27 +1181,31 @@ long int initdram(int board_type)
        denali_wait_for_dlllock();
 
 #if defined(CONFIG_DDR_DATA_EYE)
-       /* -----------------------------------------------------------+
-        * Perform data eye search if requested.
-        * ----------------------------------------------------------*/
-       program_tlb(0, CFG_SDRAM_BASE, dram_size, TLB_WORD2_I_ENABLE);
+       /*
+        * Map the first 1 MiB of memory in the TLB, and perform the data eye
+        * search.
+        */
+       program_tlb(0, CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE, TLB_WORD2_I_ENABLE);
        denali_core_search_data_eye();
        denali_sdram_register_dump();
-       remove_tlb(CFG_SDRAM_BASE, dram_size);
+       remove_tlb(CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE);
 #endif
 
 #if defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC)
-       program_tlb(0, CFG_SDRAM_BASE, dram_size, 0);
+       program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, 0);
        sync();
-       eieio();
        /* Zero the memory */
        debug("Zeroing SDRAM...");
-       dcbz_area(CFG_SDRAM_BASE, dram_size);
-       dflush();
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+       dcbz_area(CONFIG_SYS_SDRAM_BASE, dram_size - CONFIG_SYS_MEM_TOP_HIDE);
+#else
+#error Please define CONFIG_SYS_MEM_TOP_HIDE (see README) in your board config file
+#endif
+       /* Write modified dcache lines back to memory */
+       clean_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + dram_size - CONFIG_SYS_MEM_TOP_HIDE);
        debug("Completed\n");
        sync();
-       eieio();
-       remove_tlb(CFG_SDRAM_BASE, dram_size);
+       remove_tlb(CONFIG_SYS_SDRAM_BASE, dram_size);
 
 #if defined(CONFIG_DDR_ECC)
        /*
@@ -1211,7 +1215,6 @@ long int initdram(int board_type)
                u32 val;
 
                sync();
-               eieio();
                /* Clear error status */
                mfsdram(DDR0_00, val);
                mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
@@ -1229,12 +1232,11 @@ long int initdram(int board_type)
                print_mcsr();
 #endif
                sync();
-               eieio();
        }
 #endif /* defined(CONFIG_DDR_ECC) */
 #endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */
 
-       program_tlb(0, CFG_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE);
+       program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE);
        return dram_size;
 }
 
@@ -1246,7 +1248,7 @@ void board_add_ram_info(int use_default)
        if (!is_ecc_enabled()) {
                printf(" not");
        }
-       printf(" enabled, %d MHz", (2 * get_bus_freq(0)) / 1000000);
+       printf(" enabled, %ld MHz", (2 * get_bus_freq(0)) / 1000000);
 
        mfsdram(DDR0_03, val);
        printf(", CL%d)", DDR0_03_CASLAT_LIN_DECODE(val) >> 1);