mtd: denali: add Denali controller configs to Kconfig

[karo-tx-uboot.git] / doc / README.nand

diff --git a/doc/README.nand b/doc/README.nand
index b91f1985d183d0c3681567293cae7d666139a441..e29188f1ec0cd4dd97a38ddb4bb7ed85645f83fe 100644 (file)
--- a/doc/README.nand
+++ b/doc/README.nand
@@ -89,6 +89,10 @@ Commands:
 
 Configuration Options:
 
 
 Configuration Options:
 

+   CONFIG_SYS_NAND_U_BOOT_OFFS
+       NAND Offset from where SPL will read u-boot image. This is the starting
+       address of u-boot MTD partition in NAND.
+

    CONFIG_CMD_NAND
       Enables NAND support and commmands.
 
    CONFIG_CMD_NAND
       Enables NAND support and commmands.
 


@@ -190,6 +194,24 @@ Configuration Options:
        This is used by SoC platforms which do not have built-in ELM
        hardware engine required for BCH ECC correction.
 
        This is used by SoC platforms which do not have built-in ELM
        hardware engine required for BCH ECC correction.
 

+   CONFIG_SYS_NAND_BUSWIDTH_16BIT
+       Indicates that NAND device has 16-bit wide data-bus. In absence of this
+       config, bus-width of NAND device is assumed to be either 8-bit and later
+       determined by reading ONFI params.
+       Above config is useful when NAND device's bus-width information cannot
+       be determined from on-chip ONFI params, like in following scenarios:
+       - SPL boot does not support reading of ONFI parameters. This is done to
+         keep SPL code foot-print small.
+       - In current U-Boot flow using nand_init(), driver initialization
+         happens in board_nand_init() which is called before any device probe
+         (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
+         not available while configuring controller. So a static CONFIG_NAND_xx
+         is needed to know the device's bus-width in advance.
+       Some drivers using above config are:
+       drivers/mtd/nand/mxc_nand.c
+       drivers/mtd/nand/ndfc.c
+       drivers/mtd/nand/omap_gpmc.c
+

 
 Platform specific options
 =========================
 
 Platform specific options
 =========================


@@ -208,6 +230,14 @@ Platform specific options
        detection. However ECC calculation on such plaforms would still be
        done by GPMC controller.
 
        detection. However ECC calculation on such plaforms would still be
        done by GPMC controller.
 

+   CONFIG_SPL_NAND_AM33XX_BCH
+       Enables SPL-NAND driver (am335x_spl_bch.c) which supports ELM based
+        hardware ECC correction. This is useful for platforms which have ELM
+       hardware engine and use NAND boot mode.
+       Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
+       so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
+        SPL-NAND driver with software ECC correction support.
+

    CONFIG_NAND_OMAP_ECCSCHEME
        On OMAP platforms, this CONFIG specifies NAND ECC scheme.
        It can take following values:
    CONFIG_NAND_OMAP_ECCSCHEME
        On OMAP platforms, this CONFIG specifies NAND ECC scheme.
        It can take following values:


@@ -231,6 +261,48 @@ Platform specific options
                8-bit BCH code with
                - ecc calculation using GPMC hardware engine,
                - error detection using ELM hardware engine.
                8-bit BCH code with
                - ecc calculation using GPMC hardware engine,
                - error detection using ELM hardware engine.

+       OMAP_ECC_BCH16_CODE_HW
+               16-bit BCH code with
+               - ecc calculation using GPMC hardware engine,
+               - error detection using ELM hardware engine.
+
+       How to select ECC scheme on OMAP and AMxx platforms ?
+       -----------------------------------------------------
+       Though higher ECC schemes have more capability to detect and correct
+       bit-flips, but still selection of ECC scheme is dependent on following
+       - hardware engines present in SoC.
+               Some legacy OMAP SoC do not have ELM h/w engine thus such
+               SoC cannot support BCHx_HW ECC schemes.
+       - size of OOB/Spare region
+               With higher ECC schemes, more OOB/Spare area is required to
+               store ECC. So choice of ECC scheme is limited by NAND oobsize.
+
+       In general following expression can help:
+               NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
+       where
+               NAND_OOBSIZE    = number of bytes available in
+                               OOB/spare area per NAND page.
+               NAND_PAGESIZE   = bytes in main-area of NAND page.
+               ECC_BYTES       = number of ECC bytes generated to
+                               protect 512 bytes of data, which is:
+                               3 for HAM1_xx ecc schemes
+                               7 for BCH4_xx ecc schemes
+                               14 for BCH8_xx ecc schemes
+                               26 for BCH16_xx ecc schemes
+
+               example to check for BCH16 on 2K page NAND
+               NAND_PAGESIZE = 2048
+               NAND_OOBSIZE = 64
+               2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
+               Thus BCH16 cannot be supported on 2K page NAND.
+
+               However, for 4K pagesize NAND
+               NAND_PAGESIZE = 4096
+               NAND_OOBSIZE = 64
+               ECC_BYTES = 26
+               2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
+               Thus BCH16 can be supported on 4K page NAND.
+

 
 NOTE:
 =====
 
 NOTE:
 =====