CPCI4052: Remove CONFIG_SYS_LONGHELP

[karo-tx-uboot.git] / doc / README.omap3

diff --git a/doc/README.omap3 b/doc/README.omap3
index 460950dfd0efff64ddd69377d54f31ae0e6bcbff..a62c3574054d5a9cb36d918d3c35766967e81d81 100644 (file)
--- a/doc/README.omap3
+++ b/doc/README.omap3
@@ -68,6 +68,11 @@ make
 make cm_t35_config
 make
 
+* BlueLYNX-X:
+
+make omap3_mvblx_config
+make
+
 Custom commands
 ===============
 
@@ -95,33 +100,78 @@ Interfaces
 ==========
 
 gpio
+----
 
 To set a bit :
 
-       if (!omap_request_gpio(N)) {
-               omap_set_gpio_direction(N, 0);
-               omap_set_gpio_dataout(N, 1);
+       if (!gpio_request(N, "")) {
+               gpio_direction_output(N, 0);
+               gpio_set_value(N, 1);
        }
 
 To clear a bit :
 
-       if (!omap_request_gpio(N)) {
-               omap_set_gpio_direction(N, 0);
-               omap_set_gpio_dataout(N, 0);
+       if (!gpio_request(N, "")) {
+               gpio_direction_output(N, 0);
+               gpio_set_value(N, 0);
        }
 
 To read a bit :
 
-       if (!omap_request_gpio(N)) {
-               omap_set_gpio_direction(N, 1);
-               val = omap_get_gpio_datain(N);
-               omap_free_gpio(N);
+       if (!gpio_request(N, "")) {
+               gpio_direction_input(N);
+               val = gpio_get_value(N);
+               gpio_free(N);
        }
        if (val)
                printf("GPIO N is set\n");
        else
                printf("GPIO N is clear\n");
 
+dma
+---
+void omap3_dma_init(void)
+       Init the DMA module
+int omap3_dma_get_conf_chan(uint32_t chan, struct dma4_chan *config);
+       Read config of the channel
+int omap3_dma_conf_chan(uint32_t chan, struct dma4_chan *config);
+       Write config to the channel
+int omap3_dma_conf_transfer(uint32_t chan, uint32_t *src, uint32_t *dst,
+               uint32_t sze)
+       Config source, destination and size of a transfer
+int omap3_dma_wait_for_transfer(uint32_t chan)
+       Wait for a transfer to end - this hast to be called before a channel
+       or the data the channel transferd are used.
+int omap3_dma_get_revision(uint32_t *minor, uint32_t *major)
+       Read silicon Revision of the DMA module
+
+NAND
+====
+
+There are some OMAP3 devices out there with NAND attached. Due to the fact that
+OMAP3 ROM code can only handle 1-bit hamming ECC for accessing first page
+(place where SPL lives) we require this setup for u-boot at least when reading
+the second progam within SPL.  A lot of newer NAND chips however require more
+than 1-bit ECC for the pages, some can live with 1-bit for the first page. To
+handle this we can switch to another ECC algorithm after reading the payload
+within SPL.
+
+BCH8
+----
+
+To enable hardware assisted BCH8 (8-bit BCH [Bose, Chaudhuri, Hocquenghem]) on
+OMAP3 devices we can use the BCH library in lib/bch.c. To do so add CONFIG_BCH
+and set CONFIG_NAND_OMAP_ECCSCHEME=5 (refer README.nand) for selecting BCH8_SW.
+The NAND OOB layout is the same as in linux kernel, if the linux kernel BCH8
+implementation for OMAP3 works for you so the u-boot version should also.
+When you require the SPL to read with BCH8 there are two more configs to
+change:
+
+ * CONFIG_SYS_NAND_ECCPOS (must be the same as .eccpos in
+   GPMC_NAND_HW_BCH8_ECC_LAYOUT defined in
+   arch/arm/include/asm/arch-omap3/omap_gpmc.h)
+ * CONFIG_SYS_NAND_ECCSIZE must be 512
+ * CONFIG_SYS_NAND_ECCBYTES must be 13 for this BCH8 setup
 
 Acknowledgements
 ================