* Author: Jason Jin<Jason.jin@freescale.com>
* Zhang Wei<wei.zhang@freescale.com>
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*
* with the reference on libata and ahci drvier in kernel
- *
*/
#include <common.h>
#include <linux/ctype.h>
#include <ahci.h>
+static int ata_io_flush(u8 port);
+
struct ahci_probe_ent *probe_ent = NULL;
hd_driveid_t *ataid[AHCI_MAX_PORTS];
#define MAX_SATA_BLOCKS_READ_WRITE 0x80
#endif
+/* Maximum timeouts for each event */
+#define WAIT_MS_SPINUP 10000
+#define WAIT_MS_DATAIO 5000
+#define WAIT_MS_FLUSH 5000
+#define WAIT_MS_LINKUP 4
+
static inline u32 ahci_port_base(u32 base, u32 port)
{
return base + 0x100 + (port * 0x80);
#define msleep(a) udelay(a * 1000)
+static void ahci_dcache_flush_range(unsigned begin, unsigned len)
+{
+ const unsigned long start = begin;
+ const unsigned long end = start + len;
+
+ debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
+ flush_dcache_range(start, end);
+}
+
+/*
+ * SATA controller DMAs to physical RAM. Ensure data from the
+ * controller is invalidated from dcache; next access comes from
+ * physical RAM.
+ */
+static void ahci_dcache_invalidate_range(unsigned begin, unsigned len)
+{
+ const unsigned long start = begin;
+ const unsigned long end = start + len;
+
+ debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
+ invalidate_dcache_range(start, end);
+}
+
+/*
+ * Ensure data for SATA controller is flushed out of dcache and
+ * written to physical memory.
+ */
+static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
+{
+ ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
+ AHCI_PORT_PRIV_DMA_SZ);
+}
+
static int waiting_for_cmd_completed(volatile u8 *offset,
int timeout_msec,
u32 sign)
return (i < timeout_msec) ? 0 : -1;
}
+int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, u8 port)
+{
+ u32 tmp;
+ int j = 0;
+ u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio;
+
+ /*
+ * Bring up SATA link.
+ * SATA link bringup time is usually less than 1 ms; only very
+ * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
+ */
+ while (j < WAIT_MS_LINKUP) {
+ tmp = readl(port_mmio + PORT_SCR_STAT);
+ tmp &= PORT_SCR_STAT_DET_MASK;
+ if (tmp == PORT_SCR_STAT_DET_PHYRDY)
+ return 0;
+ udelay(1000);
+ j++;
+ }
+ return 1;
+}
static int ahci_host_init(struct ahci_probe_ent *probe_ent)
{
unsigned short vendor;
#endif
volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
- u32 tmp, cap_save;
- int i, j;
+ u32 tmp, cap_save, cmd;
+ int i, j, ret;
volatile u8 *port_mmio;
+ u32 port_map;
debug("ahci_host_init: start\n");
cap_save = readl(mmio + HOST_CAP);
cap_save &= ((1 << 28) | (1 << 17));
- cap_save |= (1 << 27);
+ cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
/* global controller reset */
tmp = readl(mmio + HOST_CTL);
#endif
probe_ent->cap = readl(mmio + HOST_CAP);
probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
+ port_map = probe_ent->port_map;
probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
debug("cap 0x%x port_map 0x%x n_ports %d\n",
probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
for (i = 0; i < probe_ent->n_ports; i++) {
+ if (!(port_map & (1 << i)))
+ continue;
probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
port_mmio = (u8 *) probe_ent->port[i].port_mmio;
ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i);
msleep(500);
}
- debug("Spinning up port %d... ", i);
- writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
+ /* Add the spinup command to whatever mode bits may
+ * already be on in the command register.
+ */
+ cmd = readl(port_mmio + PORT_CMD);
+ cmd |= PORT_CMD_FIS_RX;
+ cmd |= PORT_CMD_SPIN_UP;
+ writel_with_flush(cmd, port_mmio + PORT_CMD);
+
+ /* Bring up SATA link. */
+ ret = ahci_link_up(probe_ent, i);
+ if (ret) {
+ printf("SATA link %d timeout.\n", i);
+ continue;
+ } else {
+ debug("SATA link ok.\n");
+ }
+
+ /* Clear error status */
+ tmp = readl(port_mmio + PORT_SCR_ERR);
+ if (tmp)
+ writel(tmp, port_mmio + PORT_SCR_ERR);
+
+ debug("Spinning up device on SATA port %d... ", i);
j = 0;
- while (j < 1000) {
- tmp = readl(port_mmio + PORT_SCR_STAT);
- if ((tmp & 0xf) == 0x3)
+ while (j < WAIT_MS_SPINUP) {
+ tmp = readl(port_mmio + PORT_TFDATA);
+ if (!(tmp & (ATA_STAT_BUSY | ATA_STAT_DRQ)))
break;
udelay(1000);
j++;
}
- if (j == 1000)
+ printf("Target spinup took %d ms.\n", j);
+ if (j == WAIT_MS_SPINUP)
debug("timeout.\n");
else
debug("ok.\n");
/* register linkup ports */
tmp = readl(port_mmio + PORT_SCR_STAT);
- debug("Port %d status: 0x%x\n", i, tmp);
- if ((tmp & 0xf) == 0x03)
+ debug("SATA port %d status: 0x%x\n", i, tmp);
+ if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY)
probe_ent->link_port_map |= (0x01 << i);
}
memcpy((unsigned char *)pp->cmd_tbl, fis, sizeof(fis));
ahci_fill_cmd_slot(pp, cmd_fis_len);
+ ahci_dcache_flush_sata_cmd(pp);
writel(1, port_mmio + PORT_CMD_ISSUE);
readl(port_mmio + PORT_CMD_ISSUE);
- if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
+ if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
+ WAIT_MS_DATAIO, 0x1)) {
printf("set feature error on port %d!\n", port);
}
}
opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
ahci_fill_cmd_slot(pp, opts);
+ ahci_dcache_flush_sata_cmd(pp);
+ ahci_dcache_flush_range((unsigned)buf, (unsigned)buf_len);
+
writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
- if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
+ if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
+ WAIT_MS_DATAIO, 0x1)) {
printf("timeout exit!\n");
return -1;
}
+
+ ahci_dcache_invalidate_range((unsigned)buf, (unsigned)buf_len);
debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
return 0;
*/
static int ata_scsiop_inquiry(ccb *pccb)
{
- u8 hdr[] = {
+ static const u8 hdr[] = {
0,
0,
0x5, /* claim SPC-3 version compatibility */
if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), tmpid,
sizeof(hd_driveid_t), 0)) {
debug("scsi_ahci: SCSI inquiry command failure.\n");
+ free(tmpid);
return -EIO;
}
fis[0] = 0x27; /* Host to device FIS. */
fis[1] = 1 << 7; /* Command FIS. */
/* Command byte (read/write). */
- fis[2] = is_write ? ATA_CMD_WR_DMA : ATA_CMD_RD_DMA;
+ fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
while (blocks) {
u16 now_blocks; /* number of blocks per iteration */
return -EIO;
}
- /* LBA address, only support LBA28 in this driver */
+ /* LBA48 SATA command but only use 32bit address range within
+ * that. The next smaller command range (28bit) is too small.
+ */
fis[4] = (lba >> 0) & 0xff;
fis[5] = (lba >> 8) & 0xff;
fis[6] = (lba >> 16) & 0xff;
- fis[7] = ((lba >> 24) & 0xf) | 0xe0;
+ fis[7] = 1 << 6; /* device reg: set LBA mode */
+ fis[8] = ((lba >> 24) & 0xff);
+ fis[3] = 0xe0; /* features */
/* Block (sector) count */
fis[12] = (now_blocks >> 0) & 0xff;
is_write ? "WRITE" : "READ");
return -EIO;
}
+
+ /* If this transaction is a write, do a following flush.
+ * Writes in u-boot are so rare, and the logic to know when is
+ * the last write and do a flush only there is sufficiently
+ * difficult. Just do a flush after every write. This incurs,
+ * usually, one extra flush when the rare writes do happen.
+ */
+ if (is_write) {
+ if (-EIO == ata_io_flush(pccb->target))
+ return -EIO;
+ }
user_buffer += transfer_size;
user_buffer_size -= transfer_size;
blocks -= now_blocks;
break;
default:
printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
- return FALSE;
+ return false;
}
if (ret) {
debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
- return FALSE;
+ return false;
}
- return TRUE;
+ return true;
}
}
#endif
+/*
+ * In the general case of generic rotating media it makes sense to have a
+ * flush capability. It probably even makes sense in the case of SSDs because
+ * one cannot always know for sure what kind of internal cache/flush mechanism
+ * is embodied therein. At first it was planned to invoke this after the last
+ * write to disk and before rebooting. In practice, knowing, a priori, which
+ * is the last write is difficult. Because writing to the disk in u-boot is
+ * very rare, this flush command will be invoked after every block write.
+ */
+static int ata_io_flush(u8 port)
+{
+ u8 fis[20];
+ struct ahci_ioports *pp = &(probe_ent->port[port]);
+ volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
+ u32 cmd_fis_len = 5; /* five dwords */
+
+ /* Preset the FIS */
+ memset(fis, 0, 20);
+ fis[0] = 0x27; /* Host to device FIS. */
+ fis[1] = 1 << 7; /* Command FIS. */
+ fis[2] = ATA_CMD_FLUSH_EXT;
+
+ memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
+ ahci_fill_cmd_slot(pp, cmd_fis_len);
+ writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
+
+ if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
+ WAIT_MS_FLUSH, 0x1)) {
+ debug("scsi_ahci: flush command timeout on port %d.\n", port);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+
void scsi_bus_reset(void)
{
/*Not implement*/
projects / karo-tx-uboot.git / blobdiff