Merge branch 'u-boot-marvell/master' into 'u-boot-arm/master'

[karo-tx-uboot.git] / drivers / mtd / nand / fsl_elbc_nand.c

diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 0fa776ae91947541cfde27385b5b852403512122..3372b64212559cf1c9c922ec1a0f22cbea1d3c32 100644 (file)
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -5,19 +5,7 @@
  * Authors: Nick Spence <nick.spence@freescale.com>,
  *          Scott Wood <scottwood@freescale.com>
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -49,7 +37,6 @@
 
 #define MAX_BANKS 8
 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
-#define FCM_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for FCM */
 
 #define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
 
@@ -211,7 +198,8 @@ static int fsl_elbc_run_command(struct mtd_info *mtd)
        struct fsl_elbc_mtd *priv = chip->priv;
        struct fsl_elbc_ctrl *ctrl = priv->ctrl;
        fsl_lbc_t *lbc = ctrl->regs;
-       long long end_tick;
+       u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
+       u32 time_start;
        u32 ltesr;
 
        /* Setup the FMR[OP] to execute without write protection */
@@ -230,10 +218,10 @@ static int fsl_elbc_run_command(struct mtd_info *mtd)
        out_be32(&lbc->lsor, priv->bank);
 
        /* wait for FCM complete flag or timeout */
-       end_tick = usec2ticks(FCM_TIMEOUT_MSECS * 1000) + get_ticks();
+       time_start = get_timer(0);
 
        ltesr = 0;
-       while (end_tick > get_ticks()) {
+       while (get_timer(time_start) < timeo) {
                ltesr = in_be32(&lbc->ltesr);
                if (ltesr & LTESR_CC)
                        break;
@@ -573,6 +561,7 @@ static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
                       len, avail);
 }
 
+#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
 /*
  * Verify buffer against the FCM Controller Data Buffer
  */
@@ -605,6 +594,7 @@ static int fsl_elbc_verify_buf(struct mtd_info *mtd,
        ctrl->index += len;
        return i == len && ctrl->status == LTESR_CC ? 0 : -EIO;
 }
+#endif
 
 /* This function is called after Program and Erase Operations to
  * check for success or failure.
@@ -737,7 +727,9 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr)
        nand->read_byte = fsl_elbc_read_byte;
        nand->write_buf = fsl_elbc_write_buf;
        nand->read_buf = fsl_elbc_read_buf;
+#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
        nand->verify_buf = fsl_elbc_verify_buf;
+#endif
        nand->select_chip = fsl_elbc_select_chip;
        nand->cmdfunc = fsl_elbc_cmdfunc;
        nand->waitfunc = fsl_elbc_wait;
@@ -771,8 +763,12 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr)
                nand->ecc.steps = 1;
                nand->ecc.strength = 1;
        } else {
-               /* otherwise fall back to default software ECC */
+               /* otherwise fall back to software ECC */
+#if defined(CONFIG_NAND_ECC_BCH)
+               nand->ecc.mode = NAND_ECC_SOFT_BCH;
+#else
                nand->ecc.mode = NAND_ECC_SOFT;
+#endif
        }
 
        ret = nand_scan_ident(mtd, 1, NULL);