}
/* wait for the SMI register to become available */
- if (armdfec_phy_timeout(®s->smi, SMI_BUSY, FALSE)) {
+ if (armdfec_phy_timeout(®s->smi, SMI_BUSY, false)) {
printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__);
return -1;
}
writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_R, ®s->smi);
/* now wait for the data to be valid */
- if (armdfec_phy_timeout(®s->smi, SMI_R_VALID, TRUE)) {
+ if (armdfec_phy_timeout(®s->smi, SMI_R_VALID, true)) {
val = readl(®s->smi);
printf("ARMD100 FEC: (%s) PHY Read timeout, val=0x%x\n",
__func__, val);
}
/* wait for the SMI register to become available */
- if (armdfec_phy_timeout(®s->smi, SMI_BUSY, FALSE)) {
+ if (armdfec_phy_timeout(®s->smi, SMI_BUSY, false)) {
printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__);
return -1;
}
struct tx_desc *p_txdesc = darmdfec->p_txdesc;
void *p = (void *)dataptr;
int retry = PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS;
- u32 cmd_sts;
+ u32 cmd_sts, temp;
/* Copy buffer if it's misaligned */
if ((u32)dataptr & 0x07) {
p_txdesc->byte_cnt = datasize;
/* Apply send command using high priority TX queue */
- writel((u32)p_txdesc, ®s->txcdp[TXQ]);
+ temp = (u32)®s->txcdp[TXQ];
+ writel((u32)p_txdesc, temp);
writel(SDMA_CMD_TXDL | SDMA_CMD_TXDH | SDMA_CMD_ERD, ®s->sdma_cmd);
/*