Merge branch 'master' of git://git.denx.de/u-boot-usb

[karo-tx-uboot.git] / drivers / net / fec_mxc.c

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index d31001651642b2e8127e8274aee4485d87b17578..b57247032fa85aaa65ec47c9fcf7668a4cd567df 100644 (file)
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -11,6 +11,7 @@
 #include <common.h>
 #include <malloc.h>
 #include <net.h>
+#include <netdev.h>
 #include <miiphy.h>
 #include "fec_mxc.h"
 
@@ -179,13 +180,14 @@ static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr,
        return 0;
 }
 
-int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr)
+static int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr,
+                       int regAddr)
 {
        return fec_mdio_read(bus->priv, phyAddr, regAddr);
 }
 
-int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr,
-               u16 data)
+static int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr,
+                        int regAddr, u16 data)
 {
        return fec_mdio_write(bus->priv, phyAddr, regAddr, data);
 }
@@ -719,13 +721,37 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
                        break;
        }
 
-       if (!timeout)
+       if (!timeout) {
                ret = -EINVAL;
+               goto out;
+       }
 
-       invalidate_dcache_range(addr, addr + size);
-       if (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY)
+       /*
+        * The TDAR bit is cleared when the descriptors are all out from TX
+        * but on mx6solox we noticed that the READY bit is still not cleared
+        * right after TDAR.
+        * These are two distinct signals, and in IC simulation, we found that
+        * TDAR always gets cleared prior than the READY bit of last BD becomes
+        * cleared.
+        * In mx6solox, we use a later version of FEC IP. It looks like that
+        * this intrinsic behaviour of TDAR bit has changed in this newer FEC
+        * version.
+        *
+        * Fix this by polling the READY bit of BD after the TDAR polling,
+        * which covers the mx6solox case and does not harm the other SoCs.
+        */
+       timeout = FEC_XFER_TIMEOUT;
+       while (--timeout) {
+               invalidate_dcache_range(addr, addr + size);
+               if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
+                   FEC_TBD_READY))
+                       break;
+       }
+
+       if (!timeout)
                ret = -EINVAL;
 
+out:
        debug("fec_send: status 0x%x index %d ret %i\n",
                        readw(&fec->tbd_base[fec->tbd_index].status),
                        fec->tbd_index, ret);