Merge branch 'u-boot/master' into u-boot-arm/master

[karo-tx-uboot.git] / drivers / net / fec_mxc.c

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index da95e285b70db65f1f6bb709414ca5ff5ec2f8b0..e14a3598ca3e91465cafd2d613a84d807ca1ffd1 100644 (file)
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -5,20 +5,7 @@
  * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
  * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -560,7 +547,6 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
                }
                memset(fec->tbd_base, 0, size);
                fec_tbd_init(fec);
-               flush_dcache_range((unsigned)fec->tbd_base, size);
        }
 
        /*
@@ -737,6 +723,28 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
        addr = (uint32_t)fec->tbd_base;
        flush_dcache_range(addr, addr + size);
 
+       /*
+        * Below we read the DMA descriptor's last four bytes back from the
+        * DRAM. This is important in order to make sure that all WRITE
+        * operations on the bus that were triggered by previous cache FLUSH
+        * have completed.
+        *
+        * Otherwise, on MX28, it is possible to observe a corruption of the
+        * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
+        * for the bus structure of MX28. The scenario is as follows:
+        *
+        * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
+        *    to DRAM due to flush_dcache_range()
+        * 2) ARM core writes the FEC registers via AHB_ARB2
+        * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
+        *
+        * Note that 2) does sometimes finish before 1) due to reordering of
+        * WRITE accesses on the AHB bus, therefore triggering 3) before the
+        * DMA descriptor is fully written into DRAM. This results in occasional
+        * corruption of the DMA descriptor.
+        */
+       readl(addr + size - 4);
+
        /*
         * Enable SmartDMA transmit task
         */