*
* Copyright 2000 MontaVista Software Inc.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
-
+#include <errno.h>
#include <pci.h>
#undef DEBUG
struct pci_region *prefetch,
struct pci_region *io)
{
- pci_addr_t bar_response;
- pci_addr_t bar_value;
+ u32 bar_response;
pci_size_t bar_size;
u16 cmdstat = 0;
- struct pci_region *bar_res;
int bar, bar_nr = 0;
+#ifndef CONFIG_PCI_ENUM_ONLY
+ pci_addr_t bar_value;
+ struct pci_region *bar_res;
int found_mem64 = 0;
+#endif
pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
for (bar = PCI_BASE_ADDRESS_0;
bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
/* Tickle the BAR and get the response */
+#ifndef CONFIG_PCI_ENUM_ONLY
pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
+#endif
pci_hose_read_config_dword(hose, dev, bar, &bar_response);
/* If BAR is not implemented go to the next BAR */
if (!bar_response)
continue;
+#ifndef CONFIG_PCI_ENUM_ONLY
found_mem64 = 0;
+#endif
/* Check the BAR type and set our address mask */
if (bar_response & PCI_BASE_ADDRESS_SPACE) {
bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
& 0xffff) + 1;
+#ifndef CONFIG_PCI_ENUM_ONLY
bar_res = io;
+#endif
DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ", bar_nr, (u64)bar_size);
} else {
PCI_BASE_ADDRESS_MEM_TYPE_64) {
u32 bar_response_upper;
u64 bar64;
+
+#ifndef CONFIG_PCI_ENUM_ONLY
pci_hose_write_config_dword(hose, dev, bar + 4,
0xffffffff);
+#endif
pci_hose_read_config_dword(hose, dev, bar + 4,
&bar_response_upper);
bar64 = ((u64)bar_response_upper << 32) | bar_response;
bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
+#ifndef CONFIG_PCI_ENUM_ONLY
found_mem64 = 1;
+#endif
} else {
bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
}
+#ifndef CONFIG_PCI_ENUM_ONLY
if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
bar_res = prefetch;
else
bar_res = mem;
+#endif
DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%llx, ", bar_nr, (u64)bar_size);
}
+#ifndef CONFIG_PCI_ENUM_ONLY
if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
/* Write it out and update our limit */
pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
#endif
}
- cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
- PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
}
+#endif
+ cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
+ PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
DEBUGF("\n");
pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
}
+int pciauto_setup_rom(struct pci_controller *hose, pci_dev_t dev)
+{
+ pci_addr_t bar_value;
+ pci_size_t bar_size;
+ u32 bar_response;
+ u16 cmdstat = 0;
+
+ pci_hose_write_config_dword(hose, dev, PCI_ROM_ADDRESS, 0xfffffffe);
+ pci_hose_read_config_dword(hose, dev, PCI_ROM_ADDRESS, &bar_response);
+ if (!bar_response)
+ return -ENOENT;
+
+ bar_size = -(bar_response & ~1);
+ DEBUGF("PCI Autoconfig: ROM, size=%#x, ", bar_size);
+ if (pciauto_region_allocate(hose->pci_mem, bar_size, &bar_value) == 0) {
+ pci_hose_write_config_dword(hose, dev, PCI_ROM_ADDRESS,
+ bar_value);
+ }
+ DEBUGF("\n");
+ pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
+ cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+ pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
+
+ return 0;
+}
+
void pciauto_prescan_setup_bridge(struct pci_controller *hose,
pci_dev_t dev, int sub_bus)
{
struct pci_region *pci_mem = hose->pci_mem;
struct pci_region *pci_prefetch = hose->pci_prefetch;
struct pci_region *pci_io = hose->pci_io;
- u16 cmdstat;
+ u16 cmdstat, prefechable_64;
pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
+ pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
+ &prefechable_64);
+ prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
/* Configure bus number registers */
pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
/* Set up memory and I/O filter limits, assume 32-bit I/O space */
pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
(pci_prefetch->bus_lower & 0xfff00000) >> 16);
+ if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
+#ifdef CONFIG_SYS_PCI_64BIT
+ pci_hose_write_config_dword(hose, dev,
+ PCI_PREF_BASE_UPPER32,
+ pci_prefetch->bus_lower >> 32);
+#else
+ pci_hose_write_config_dword(hose, dev,
+ PCI_PREF_BASE_UPPER32,
+ 0x0);
+#endif
cmdstat |= PCI_COMMAND_MEMORY;
} else {
/* We don't support prefetchable memory for now, so disable */
pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
+ if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
+ pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0);
+ pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0);
+ }
}
if (pci_io) {
}
if (pci_prefetch) {
+ u16 prefechable_64;
+
+ pci_hose_read_config_word(hose, dev,
+ PCI_PREF_MEMORY_LIMIT,
+ &prefechable_64);
+ prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
+
/* Round memory allocator to 1MB boundary */
pciauto_region_align(pci_prefetch, 0x100000);
pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
(pci_prefetch->bus_lower - 1) >> 16);
+ if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
+#ifdef CONFIG_SYS_PCI_64BIT
+ pci_hose_write_config_dword(hose, dev,
+ PCI_PREF_LIMIT_UPPER32,
+ (pci_prefetch->bus_lower - 1) >> 32);
+#else
+ pci_hose_write_config_dword(hose, dev,
+ PCI_PREF_LIMIT_UPPER32,
+ 0x0);
+#endif
}
if (pci_io) {
{
int i;
- hose->pci_io = hose->pci_mem = NULL;
+ hose->pci_io = hose->pci_mem = hose->pci_prefetch = NULL;
for (i = 0; i < hose->region_count; i++) {
switch(hose->regions[i].flags) {
pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
switch (class) {
- case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
- DEBUGF("PCI AutoConfig: Found PowerPC device\n");
- pciauto_setup_device(hose, dev, 6, hose->pci_mem,
- hose->pci_prefetch, hose->pci_io);
- break;
-
case PCI_CLASS_BRIDGE_PCI:
- hose->current_busno++;
+ DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n",
+ PCI_DEV(dev));
+
pciauto_setup_device(hose, dev, 2, hose->pci_mem,
hose->pci_prefetch, hose->pci_io);
- DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));
-
+#ifdef CONFIG_DM_PCI
+ n = dm_pci_hose_probe_bus(hose, dev);
+ if (n < 0)
+ return n;
+ sub_bus = (unsigned int)n;
+#else
/* Passing in current_busno allows for sibling P2P bridges */
+ hose->current_busno++;
pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
/*
* need to figure out if this is a subordinate bridge on the bus
n = pci_hose_scan_bus(hose, hose->current_busno);
/* figure out the deepest we've gone for this leg */
- sub_bus = max(n, sub_bus);
+ sub_bus = max((unsigned int)n, sub_bus);
pciauto_postscan_setup_bridge(hose, dev, sub_bus);
sub_bus = hose->current_busno;
+#endif
break;
case PCI_CLASS_STORAGE_IDE:
DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
PCI_DEV(dev));
+#ifndef CONFIG_DM_PCI
hose->current_busno++;
+#endif
break;
#if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
hose->pci_prefetch, hose->pci_io);
break;
#endif
+
+ case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
+ DEBUGF("PCI AutoConfig: Found PowerPC device\n");
+
default:
pciauto_setup_device(hose, dev, 6, hose->pci_mem,
hose->pci_prefetch, hose->pci_io);
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