sunxi_nand_spl: Properly config page-size in the nand ctl register

[karo-tx-uboot.git] / drivers / qe / uec_phy.h

diff --git a/drivers/qe/uec_phy.h b/drivers/qe/uec_phy.h
index e59a940e0dd4fdc2deb6178139a7f363e513d1ed..11cbc253b8e140a2e50f9b2c851f4d1cd146b2ba 100644 (file)
--- a/drivers/qe/uec_phy.h
+++ b/drivers/qe/uec_phy.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2005 Freescale Semiconductor, Inc.
+ * Copyright (C) 2005, 2011 Freescale Semiconductor, Inc.
  *
  * Author: Shlomi Gridish <gridish@freescale.com>
  *
@@ -7,11 +7,7 @@
  *             Driver for UEC on QE
  *             Based on 8260_io/fcc_enet.c
  *
- * This program is free software; you can redistribute it and/or modify it
- * under  the terms of the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 #ifndef __UEC_PHY_H__
 #define __UEC_PHY_H__
@@ -24,11 +20,6 @@
 
 #define UGETH_AN_TIMEOUT       2000
 
-/* 1000BT control (Marvell & BCM54xx at least) */
-#define MII_1000BASETCONTROL                 0x09
-#define MII_1000BASETCONTROL_FULLDUPLEXCAP    0x0200
-#define MII_1000BASETCONTROL_HALFDUPLEXCAP    0x0100
-
 /* Cicada Extended Control Register 1 */
 #define MII_CIS8201_EXT_CON1       0x17
 #define MII_CIS8201_EXTCON1_INIT    0x0000
@@ -72,6 +63,14 @@
 #define MII_M1011_IMASK_INIT           0x6400
 #define MII_M1011_IMASK_CLEAR          0x0000
 
+/* 88E1111 PHY Register */
+#define MII_M1111_PHY_EXT_CR            0x14
+#define MII_M1111_RX_DELAY              0x80
+#define MII_M1111_TX_DELAY              0x2
+#define MII_M1111_PHY_EXT_SR            0x1b
+#define MII_M1111_HWCFG_MODE_MASK       0xf
+#define MII_M1111_HWCFG_MODE_RGMII      0xb
+
 #define MII_DM9161_SCR                 0x10
 #define MII_DM9161_SCR_INIT            0x0610
 #define MII_DM9161_SCR_RMII_INIT       0x0710
@@ -156,24 +155,6 @@
 #define ADVERTISED_BNC                 (1 << 11)
 #define ADVERTISED_10000baseT_Full     (1 << 12)
 
-/* Advertisement control register. */
-#define ADVERTISE_SLCT         0x001f  /* Selector bits               */
-#define ADVERTISE_CSMA         0x0001  /* Only selector supported     */
-#define ADVERTISE_10HALF       0x0020  /* Try for 10mbps half-duplex  */
-#define ADVERTISE_10FULL       0x0040  /* Try for 10mbps full-duplex  */
-#define ADVERTISE_100HALF      0x0080  /* Try for 100mbps half-duplex */
-#define ADVERTISE_100FULL      0x0100  /* Try for 100mbps full-duplex */
-#define ADVERTISE_100BASE4     0x0200  /* Try for 100mbps 4k packets  */
-#define ADVERTISE_RESV         0x1c00  /* Unused...                   */
-#define ADVERTISE_RFAULT       0x2000  /* Say we can detect faults    */
-#define ADVERTISE_LPACK                0x4000  /* Ack link partners response  */
-#define ADVERTISE_NPAGE                0x8000  /* Next page bit               */
-
-#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
-                       ADVERTISE_CSMA)
-#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
-                      ADVERTISE_100HALF | ADVERTISE_100FULL)
-
 /* Taken from mii_if_info and sungem_phy.h */
 struct uec_mii_info {
        /* Information about the PHY type */