ARM: cache: implement a default weak flush_cache() function

[karo-tx-uboot.git] / drivers / usb / host / ehci-mxc.c

diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index 8633cab940c630df13c63f17fe6e0a106219dda6..ded991fa34375b458163321cf3b5c33ed937ffbe 100644 (file)
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -1,19 +1,7 @@
 /*
  * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
  *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software Foundation,
- * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 
@@ -79,7 +67,7 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
        unsigned int v;
 
        v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
-#if defined(CONFIG_MX25)
+#if defined(CONFIG_SOC_MX25)
        switch (port) {
        case 0: /* OTG port */
                v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT |
@@ -128,7 +116,7 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
        default:
                return -EINVAL;
        }
-#elif defined(CONFIG_MX31)
+#elif defined(CONFIG_SOC_MX31)
        switch (port) {
        case 0: /* OTG port */
                v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
@@ -163,7 +151,7 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
        default:
                return -EINVAL;
        }
-#elif defined(CONFIG_MX35)
+#elif defined(CONFIG_SOC_MX35)
        switch (port) {
        case 0: /* OTG port */
                v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT |
@@ -220,10 +208,11 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
        return 0;
 }
 
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+               struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
        struct usb_ehci *ehci;
-#ifdef CONFIG_MX31
+#ifdef CONFIG_SOC_MX31
        struct clock_control_regs *sc_regs =
                (struct clock_control_regs *)CCM_BASE;
 
@@ -241,7 +230,7 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
        setbits_le32(&ehci->usbmode, CM_HOST);
        __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
        mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
-#ifdef CONFIG_MX35
+#ifdef CONFIG_SOC_MX35
        /* Workaround for ENGcm11601 */
        __raw_writel(0, &ehci->sbuscfg);
 #endif