+/* IRQ handler for version 2 of LCDC */
+static u32 lcdc_irq_handler_rev02(void)
+{
+ u32 ret = 0;
+ struct da8xx_fb_par *par = da8xx_fb_info->par;
+ u32 stat = lcdc_read(&da8xx_fb_reg_base->masked_stat);
+
+ debug("%s: stat=%08x\n", __func__, stat);
+
+ if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
+ debug("LCD_SYNC_LOST\n");
+ lcd_disable_raster();
+ lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
+ lcd_enable_raster();
+ ret = LCD_SYNC_LOST;
+ } else if (stat & LCD_PL_LOAD_DONE) {
+ debug("LCD_PL_LOAD_DONE\n");
+ /*
+ * Must disable raster before changing state of any control bit.
+ * And also must be disabled before clearing the PL loading
+ * interrupt via the following write to the status register. If
+ * this is done after then one gets multiple PL done interrupts.
+ */
+ lcd_disable_raster();
+
+ lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
+
+ /* Disable PL completion inerrupt */
+ lcdc_write(LCD_V2_PL_INT_ENA,
+ &da8xx_fb_reg_base->int_enable_clr);
+
+ /* Setup and start data loading mode */
+ lcd_blit(LOAD_DATA, par);
+ ret = LCD_PL_LOAD_DONE;
+ } else if (stat & (LCD_END_OF_FRAME0 | LCD_END_OF_FRAME1)) {
+ par->vsync_flag = 1;
+ lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
+
+ if (stat & LCD_END_OF_FRAME0) {
+ debug("LCD_END_OF_FRAME0\n");
+
+ lcdc_write(par->dma_start,
+ &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
+ lcdc_write(par->dma_end,
+ &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
+ }
+ if (stat & LCD_END_OF_FRAME1) {
+ debug("LCD_END_OF_FRAME1\n");
+ lcdc_write(par->dma_start,
+ &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
+ lcdc_write(par->dma_end,
+ &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
+ par->vsync_flag = 1;
+ }
+ ret = (stat & LCD_END_OF_FRAME0) ?
+ LCD_END_OF_FRAME0 : LCD_END_OF_FRAME1;
+ }
+ lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
+ return ret;
+}
+
+static u32 lcdc_irq_handler_rev01(void)