static struct clk ipu_clk = {
.name = "ipu_clk",
+#if defined(CONFIG_MX51)
.rate = 133000000,
+#elif defined(CONFIG_MX53)
+ .rate = 216000000,
+#endif
.enable_reg = (u32 *)(MXC_CCM_BASE +
offsetof(struct mxc_ccm_reg, CCGR5)),
.enable_shift = MXC_CCM_CCGR5_CG5_OFFSET,
.enable = clk_ipu_enable,
.disable = clk_ipu_disable,
- .usecount = 0,
};
/* Globals */
* Fractional part is 4 bits,
* so simply multiply by 2^4 to get fractional part.
*/
- tmp = (clk->parent->rate * 16);
+ tmp = clk->parent->rate * 16;
div = tmp / rate;
if (div < 0x10) /* Min DI disp clock divider is 1 */
u32 disp_gen = __raw_readl(IPU_DISP_GEN);
disp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE;
__raw_writel(disp_gen, IPU_DISP_GEN);
-
}
static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent)
static struct clk pixel_clk[] = {
{
- .name = "pixel_clk",
- .id = 0,
- .recalc = ipu_pixel_clk_recalc,
- .set_rate = ipu_pixel_clk_set_rate,
- .round_rate = ipu_pixel_clk_round_rate,
- .set_parent = ipu_pixel_clk_set_parent,
- .enable = ipu_pixel_clk_enable,
- .disable = ipu_pixel_clk_disable,
- .usecount = 0,
+ .name = "pixel_clk",
+ .id = 0,
+ .recalc = ipu_pixel_clk_recalc,
+ .set_rate = ipu_pixel_clk_set_rate,
+ .round_rate = ipu_pixel_clk_round_rate,
+ .set_parent = ipu_pixel_clk_set_parent,
+ .enable = ipu_pixel_clk_enable,
+ .disable = ipu_pixel_clk_disable,
},
{
- .name = "pixel_clk",
- .id = 1,
- .recalc = ipu_pixel_clk_recalc,
- .set_rate = ipu_pixel_clk_set_rate,
- .round_rate = ipu_pixel_clk_round_rate,
- .set_parent = ipu_pixel_clk_set_parent,
- .enable = ipu_pixel_clk_enable,
- .disable = ipu_pixel_clk_disable,
- .usecount = 0,
+ .name = "pixel_clk",
+ .id = 1,
+ .recalc = ipu_pixel_clk_recalc,
+ .set_rate = ipu_pixel_clk_set_rate,
+ .round_rate = ipu_pixel_clk_round_rate,
+ .set_parent = ipu_pixel_clk_set_parent,
+ .enable = ipu_pixel_clk_enable,
+ .disable = ipu_pixel_clk_disable,
},
};
int ipu_probe(void)
{
unsigned long ipu_base;
+#ifdef CONFIG_MX51
u32 temp;
-
u32 *reg_hsc_mcd = (u32 *)MIPI_HSC_BASE_ADDR;
u32 *reg_hsc_mxt_conf = (u32 *)(MIPI_HSC_BASE_ADDR + 0x800);
temp = __raw_readl(reg_hsc_mxt_conf);
__raw_writel(temp | 0x10000, reg_hsc_mxt_conf);
-
+#endif
ipu_base = IPU_CTRL_BASE_ADDR;
ipu_cpmem_base = (u32 *)(ipu_base + IPU_CPMEM_REG_BASE);
ipu_dc_tmpl_reg = (u32 *)(ipu_base + IPU_DC_TMPL_REG_BASE);
void ipu_dump_registers(void)
{
- debug("IPU_CONF = \t0x%08X\n", __raw_readl(IPU_CONF));
- debug("IDMAC_CONF = \t0x%08X\n", __raw_readl(IDMAC_CONF));
- debug("IDMAC_CHA_EN1 = \t0x%08X\n",
+ debug("IPU_CONF 0x%08X\n", __raw_readl(IPU_CONF));
+ debug("IDMAC_CONF 0x%08X\n", __raw_readl(IDMAC_CONF));
+ debug("IDMAC_CHA_EN1 0x%08X\n",
__raw_readl(IDMAC_CHA_EN(0)));
- debug("IDMAC_CHA_EN2 = \t0x%08X\n",
+ debug("IDMAC_CHA_EN2 0x%08X\n",
__raw_readl(IDMAC_CHA_EN(32)));
- debug("IDMAC_CHA_PRI1 = \t0x%08X\n",
+ debug("IDMAC_CHA_PRI1 0x%08X\n",
__raw_readl(IDMAC_CHA_PRI(0)));
- debug("IDMAC_CHA_PRI2 = \t0x%08X\n",
+ debug("IDMAC_CHA_PRI2 0x%08X\n",
__raw_readl(IDMAC_CHA_PRI(32)));
- debug("IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
+ debug("IPU_CHA_DB_MODE_SEL0 0x%08X\n",
__raw_readl(IPU_CHA_DB_MODE_SEL(0)));
- debug("IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
+ debug("IPU_CHA_DB_MODE_SEL1 0x%08X\n",
__raw_readl(IPU_CHA_DB_MODE_SEL(32)));
- debug("DMFC_WR_CHAN = \t0x%08X\n",
+ debug("DMFC_WR_CHAN 0x%08X\n",
__raw_readl(DMFC_WR_CHAN));
- debug("DMFC_WR_CHAN_DEF = \t0x%08X\n",
+ debug("DMFC_WR_CHAN_DEF 0x%08X\n",
__raw_readl(DMFC_WR_CHAN_DEF));
- debug("DMFC_DP_CHAN = \t0x%08X\n",
+ debug("DMFC_DP_CHAN 0x%08X\n",
__raw_readl(DMFC_DP_CHAN));
- debug("DMFC_DP_CHAN_DEF = \t0x%08X\n",
+ debug("DMFC_DP_CHAN_DEF 0x%08X\n",
__raw_readl(DMFC_DP_CHAN_DEF));
- debug("DMFC_IC_CTRL = \t0x%08X\n",
+ debug("DMFC_IC_CTRL 0x%08X\n",
__raw_readl(DMFC_IC_CTRL));
- debug("IPU_FS_PROC_FLOW1 = \t0x%08X\n",
+ debug("IPU_FS_PROC_FLOW1 0x%08X\n",
__raw_readl(IPU_FS_PROC_FLOW1));
- debug("IPU_FS_PROC_FLOW2 = \t0x%08X\n",
+ debug("IPU_FS_PROC_FLOW2 0x%08X\n",
__raw_readl(IPU_FS_PROC_FLOW2));
- debug("IPU_FS_PROC_FLOW3 = \t0x%08X\n",
+ debug("IPU_FS_PROC_FLOW3 0x%08X\n",
__raw_readl(IPU_FS_PROC_FLOW3));
- debug("IPU_FS_DISP_FLOW1 = \t0x%08X\n",
+ debug("IPU_FS_DISP_FLOW1 0x%08X\n",
__raw_readl(IPU_FS_DISP_FLOW1));
}
u_offset = (u == 0) ? stride * height : u;
break;
default:
- puts("mxc ipu: unimplemented pixel format\n");
- break;
+ printf("mxc ipu: unimplemented pixel format: %08x\n",
+ pixel_fmt);
}
stride = width * bytes_per_pixel(pixel_fmt);
if (stride % 4) {
- printf(
- "Stride not 32-bit aligned, stride = %d\n", stride);
+ printf("Stride not 32-bit aligned, stride = %d\n", stride);
return -EINVAL;
}
/* Build parameter memory data for DMA channel */
case IPU_PIX_FMT_YUV420P:
case IPU_PIX_FMT_YUV422P:
return 1;
- break;
case IPU_PIX_FMT_RGB565:
case IPU_PIX_FMT_YUYV:
case IPU_PIX_FMT_UYVY:
return 2;
- break;
case IPU_PIX_FMT_BGR24:
case IPU_PIX_FMT_RGB24:
return 3;
- break;
case IPU_PIX_FMT_GENERIC_32: /*generic data */
case IPU_PIX_FMT_BGR32:
case IPU_PIX_FMT_BGRA32:
case IPU_PIX_FMT_RGBA32:
case IPU_PIX_FMT_ABGR32:
return 4;
- break;
default:
return 1;
- break;
}
return 0;
}
case IPU_PIX_FMT_LVDS666:
case IPU_PIX_FMT_LVDS888:
return RGB;
- break;
default:
return YCbCr;
- break;
}
return RGB;
}