arm: mxs: Add MXS LCDIF driver

[karo-tx-uboot.git] / drivers / video / ipu_disp.c

diff --git a/drivers/video/ipu_disp.c b/drivers/video/ipu_disp.c
index 11cf98d3d5ace6d76b2179b9f5c28f6a4261b972..b4116df8ca1c8e7d771a52c12fc0bed40b160575 100644 (file)
--- a/drivers/video/ipu_disp.c
+++ b/drivers/video/ipu_disp.c
@@ -64,6 +64,7 @@ static int dmfc_size_28, dmfc_size_29, dmfc_size_24, dmfc_size_27, dmfc_size_23;
 int g_di1_tvout;
 
 extern struct clk *g_ipu_clk;
+extern struct clk *g_ldb_clk;
 extern struct clk *g_di_clk[2];
 extern struct clk *g_pixel_clk[2];
 
@@ -399,29 +400,29 @@ void ipu_dp_csc_setup(int dp, struct dp_csc_param_t dp_csc_param,
        const int (*coeff)[5][3];
 
        if (dp_csc_param.mode >= 0) {
-               reg = __raw_readl(DP_COM_CONF(dp));
+               reg = __raw_readl(DP_COM_CONF());
                reg &= ~DP_COM_CONF_CSC_DEF_MASK;
                reg |= dp_csc_param.mode;
-               __raw_writel(reg, DP_COM_CONF(dp));
+               __raw_writel(reg, DP_COM_CONF());
        }
 
        coeff = dp_csc_param.coeff;
 
        if (coeff) {
                __raw_writel(mask_a((*coeff)[0][0]) |
-                               (mask_a((*coeff)[0][1]) << 16), DP_CSC_A_0(dp));
+                               (mask_a((*coeff)[0][1]) << 16), DP_CSC_A_0());
                __raw_writel(mask_a((*coeff)[0][2]) |
-                               (mask_a((*coeff)[1][0]) << 16), DP_CSC_A_1(dp));
+                               (mask_a((*coeff)[1][0]) << 16), DP_CSC_A_1());
                __raw_writel(mask_a((*coeff)[1][1]) |
-                               (mask_a((*coeff)[1][2]) << 16), DP_CSC_A_2(dp));
+                               (mask_a((*coeff)[1][2]) << 16), DP_CSC_A_2());
                __raw_writel(mask_a((*coeff)[2][0]) |
-                               (mask_a((*coeff)[2][1]) << 16), DP_CSC_A_3(dp));
+                               (mask_a((*coeff)[2][1]) << 16), DP_CSC_A_3());
                __raw_writel(mask_a((*coeff)[2][2]) |
                                (mask_b((*coeff)[3][0]) << 16) |
-                               ((*coeff)[4][0] << 30), DP_CSC_0(dp));
+                               ((*coeff)[4][0] << 30), DP_CSC_0());
                __raw_writel(mask_b((*coeff)[3][1]) | ((*coeff)[4][1] << 14) |
                                (mask_b((*coeff)[3][2]) << 16) |
-                               ((*coeff)[4][2] << 30), DP_CSC_1(dp));
+                               ((*coeff)[4][2] << 30), DP_CSC_1());
        }
 
        if (srm_mode_update) {
@@ -481,7 +482,7 @@ int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,
        }
 
        /* Transform color key from rgb to yuv if CSC is enabled */
-       reg = __raw_readl(DP_COM_CONF(dp));
+       reg = __raw_readl(DP_COM_CONF());
        if (color_key_4rgb && (reg & DP_COM_CONF_GWCKE) &&
                (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) ||
                ((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) ||
@@ -489,7 +490,7 @@ int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,
                ((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB)))) {
                int red, green, blue;
                int y, u, v;
-               uint32_t color_key = __raw_readl(DP_GRAPH_WIND_CTRL(dp)) &
+               uint32_t color_key = __raw_readl(DP_GRAPH_WIND_CTRL()) &
                        0xFFFFFFL;
 
                debug("_ipu_dp_init color key 0x%x need change to yuv fmt!\n",
@@ -504,8 +505,8 @@ int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,
                v = rgb_to_yuv(2, red, green, blue);
                color_key = (y << 16) | (u << 8) | v;
 
-               reg = __raw_readl(DP_GRAPH_WIND_CTRL(dp)) & 0xFF000000L;
-               __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL(dp));
+               reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0xFF000000L;
+               __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL());
                color_key_4rgb = 0;
 
                debug("_ipu_dp_init color key change to yuv fmt 0x%x!\n",
@@ -648,8 +649,8 @@ void ipu_dp_dc_enable(ipu_channel_t channel)
 
        if (channel == MEM_FG_SYNC) {
                /* Enable FG channel */
-               reg = __raw_readl(DP_COM_CONF(DP_SYNC));
-               __raw_writel(reg | DP_COM_CONF_FG_EN, DP_COM_CONF(DP_SYNC));
+               reg = __raw_readl(DP_COM_CONF());
+               __raw_writel(reg | DP_COM_CONF_FG_EN, DP_COM_CONF());
 
                reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
                __raw_writel(reg, IPU_SRM_PRI2);
@@ -692,13 +693,13 @@ void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap)
                /* Disable FG channel */
                dc_chan = 5;
 
-               reg = __raw_readl(DP_COM_CONF(DP_SYNC));
+               reg = __raw_readl(DP_COM_CONF());
                csc = reg & DP_COM_CONF_CSC_DEF_MASK;
                if (csc == DP_COM_CONF_CSC_DEF_FG)
                        reg &= ~DP_COM_CONF_CSC_DEF_MASK;
 
                reg &= ~DP_COM_CONF_FG_EN;
-               __raw_writel(reg, DP_COM_CONF(DP_SYNC));
+               __raw_writel(reg, DP_COM_CONF());
 
                reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
                __raw_writel(reg, IPU_SRM_PRI2);
@@ -941,7 +942,7 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk,
                                udelay(10000);
                        }
                }
-               clk_set_parent(g_pixel_clk[disp], g_di_clk[disp]);
+               clk_set_parent(g_pixel_clk[disp], g_ldb_clk);
        } else {
                if (clk_get_usecount(g_pixel_clk[disp]) != 0)
                        clk_set_parent(g_pixel_clk[disp], g_ipu_clk);
@@ -1234,17 +1235,12 @@ int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,
                                  uint8_t alpha)
 {
        uint32_t reg;
-       uint32_t flow;
 
        unsigned char bg_chan;
 
-       if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC)
-               flow = DP_SYNC;
-       else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0)
-               flow = DP_ASYNC0;
-       else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)
-               flow = DP_ASYNC1;
-       else
+       if (!((channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) ||
+               (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) ||
+               (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)))
                return -EINVAL;
 
        if (channel == MEM_BG_SYNC || channel == MEM_BG_ASYNC0 ||
@@ -1257,23 +1253,23 @@ int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,
                clk_enable(g_ipu_clk);
 
        if (bg_chan) {
-               reg = __raw_readl(DP_COM_CONF(flow));
-               __raw_writel(reg & ~DP_COM_CONF_GWSEL, DP_COM_CONF(flow));
+               reg = __raw_readl(DP_COM_CONF());
+               __raw_writel(reg & ~DP_COM_CONF_GWSEL, DP_COM_CONF());
        } else {
-               reg = __raw_readl(DP_COM_CONF(flow));
-               __raw_writel(reg | DP_COM_CONF_GWSEL, DP_COM_CONF(flow));
+               reg = __raw_readl(DP_COM_CONF());
+               __raw_writel(reg | DP_COM_CONF_GWSEL, DP_COM_CONF());
        }
 
        if (enable) {
-               reg = __raw_readl(DP_GRAPH_WIND_CTRL(flow)) & 0x00FFFFFFL;
+               reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0x00FFFFFFL;
                __raw_writel(reg | ((uint32_t) alpha << 24),
-                            DP_GRAPH_WIND_CTRL(flow));
+                            DP_GRAPH_WIND_CTRL());
 
-               reg = __raw_readl(DP_COM_CONF(flow));
-               __raw_writel(reg | DP_COM_CONF_GWAM, DP_COM_CONF(flow));
+               reg = __raw_readl(DP_COM_CONF());
+               __raw_writel(reg | DP_COM_CONF_GWAM, DP_COM_CONF());
        } else {
-               reg = __raw_readl(DP_COM_CONF(flow));
-               __raw_writel(reg & ~DP_COM_CONF_GWAM, DP_COM_CONF(flow));
+               reg = __raw_readl(DP_COM_CONF());
+               __raw_writel(reg & ~DP_COM_CONF_GWAM, DP_COM_CONF());
        }
 
        reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
@@ -1299,17 +1295,13 @@ int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,
 int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,
                               uint32_t color_key)
 {
-       uint32_t reg, flow;
+       uint32_t reg;
        int y, u, v;
        int red, green, blue;
 
-       if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC)
-               flow = DP_SYNC;
-       else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0)
-               flow = DP_ASYNC0;
-       else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)
-               flow = DP_ASYNC1;
-       else
+       if (!((channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) ||
+               (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) ||
+               (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)))
                return -EINVAL;
 
        if (!g_ipu_clk_enabled)
@@ -1339,14 +1331,14 @@ int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,
        }
 
        if (enable) {
-               reg = __raw_readl(DP_GRAPH_WIND_CTRL(flow)) & 0xFF000000L;
-               __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL(flow));
+               reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0xFF000000L;
+               __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL());
 
-               reg = __raw_readl(DP_COM_CONF(flow));
-               __raw_writel(reg | DP_COM_CONF_GWCKE, DP_COM_CONF(flow));
+               reg = __raw_readl(DP_COM_CONF());
+               __raw_writel(reg | DP_COM_CONF_GWCKE, DP_COM_CONF());
        } else {
-               reg = __raw_readl(DP_COM_CONF(flow));
-               __raw_writel(reg & ~DP_COM_CONF_GWCKE, DP_COM_CONF(flow));
+               reg = __raw_readl(DP_COM_CONF());
+               __raw_writel(reg & ~DP_COM_CONF_GWCKE, DP_COM_CONF());
        }
 
        reg = __raw_readl(IPU_SRM_PRI2) | 0x8;