add leading zeroes to some bit masks for consistency

[karo-tx-uboot.git] / drivers / video / ipu_regs.h

diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h
index 36f07bbee3368c01acf64003f415545c51bdaaf9..d89d280b4f1ac3885ed4b13cee8de9b4119451b3 100644 (file)
--- a/drivers/video/ipu_regs.h
+++ b/drivers/video/ipu_regs.h
@@ -97,7 +97,7 @@ enum {
        DI_DW_GEN_ACCESS_SIZE_OFFSET = 24,
        DI_DW_GEN_COMPONENT_SIZE_OFFSET = 16,
 
-       DI_GEN_DI_CLK_EXT = 0x100000,
+       DI_GEN_DI_CLK_EXT = 0x00100000,
        DI_GEN_POLARITY_1 = 0x00000001,
        DI_GEN_POLARITY_2 = 0x00000002,
        DI_GEN_POLARITY_3 = 0x00000004,
@@ -106,7 +106,7 @@ enum {
        DI_GEN_POLARITY_6 = 0x00000020,
        DI_GEN_POLARITY_7 = 0x00000040,
        DI_GEN_POLARITY_8 = 0x00000080,
-       DI_GEN_POL_CLK = 0x20000,
+       DI_GEN_POL_CLK    = 0x00020000,
 
        DI_POL_DRDY_DATA_POLARITY = 0x00000080,
        DI_POL_DRDY_POLARITY_15 = 0x00000010,
@@ -402,15 +402,15 @@ static inline struct ipu_dc_ch *dc_ch_offset(int ch)
 
 #define DP_REG                 ((struct ipu_dp *)(IPU_CTRL_BASE_ADDR + \
                                IPU_DP_REG_BASE))
-#define DP_COM_CONF(flow)      (&DP_REG->com_conf_sync)
-#define DP_GRAPH_WIND_CTRL(flow) (&DP_REG->graph_wind_ctrl_sync)
-#define DP_CSC_A_0(flow)       (&DP_REG->csca_sync[0])
-#define DP_CSC_A_1(flow)       (&DP_REG->csca_sync[1])
-#define DP_CSC_A_2(flow)       (&DP_REG->csca_sync[2])
-#define DP_CSC_A_3(flow)       (&DP_REG->csca_sync[3])
-
-#define DP_CSC_0(flow)         (&DP_REG->csc_sync[0])
-#define DP_CSC_1(flow)         (&DP_REG->csc_sync[1])
+#define DP_COM_CONF()          (&DP_REG->com_conf_sync)
+#define DP_GRAPH_WIND_CTRL()   (&DP_REG->graph_wind_ctrl_sync)
+#define DP_CSC_A_0()           (&DP_REG->csca_sync[0])
+#define DP_CSC_A_1()           (&DP_REG->csca_sync[1])
+#define DP_CSC_A_2()           (&DP_REG->csca_sync[2])
+#define DP_CSC_A_3()           (&DP_REG->csca_sync[3])
+
+#define DP_CSC_0()             (&DP_REG->csc_sync[0])
+#define DP_CSC_1()             (&DP_REG->csc_sync[1])
 
 /* DC template opcodes */
 #define WROD(lf)               (0x18 | (lf << 1))