Merge branch 'master' of git://git.denx.de/u-boot-nds32

[karo-tx-uboot.git] / include / ahci.h

diff --git a/include/ahci.h b/include/ahci.h
index 80701e298cf8d40d77ab5ac641e4c4fd49fe4929..78a8c55f7ba736355e425b28a3adf5f14d563534 100644 (file)
--- a/include/ahci.h
+++ b/include/ahci.h
@@ -1,39 +1,25 @@
 /*
- * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
  * Author: Jason Jin<Jason.jin@freescale.com>
  *         Zhang Wei<wei.zhang@freescale.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 #ifndef _AHCI_H_
 #define _AHCI_H_
 
+#include <pci.h>
+
 #define AHCI_PCI_BAR           0x24
 #define AHCI_MAX_SG            56 /* hardware max is 64K */
 #define AHCI_CMD_SLOT_SZ       32
+#define AHCI_MAX_CMD_SLOT      32
 #define AHCI_RX_FIS_SZ         256
 #define AHCI_CMD_TBL_HDR       0x80
 #define AHCI_CMD_TBL_CDB       0x40
 #define AHCI_CMD_TBL_SZ                AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16)
-#define AHCI_PORT_PRIV_DMA_SZ  AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ      \
-                               + AHCI_RX_FIS_SZ
+#define AHCI_PORT_PRIV_DMA_SZ  (AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT + \
+                               AHCI_CMD_TBL_SZ + AHCI_RX_FIS_SZ)
 #define AHCI_CMD_ATAPI         (1 << 5)
 #define AHCI_CMD_WRITE         (1 << 6)
 #define AHCI_CMD_PREFETCH      (1 << 7)
@@ -48,6 +34,7 @@
 #define HOST_IRQ_STAT          0x08 /* interrupt status */
 #define HOST_PORTS_IMPL                0x0c /* bitmap of implemented ports */
 #define HOST_VERSION           0x10 /* AHCI spec. version compliancy */
+#define HOST_CAP2              0x24 /* host capabilities, extended */
 
 /* HOST_CTL bits */
 #define HOST_RESET             (1 << 0)  /* reset controller; self-clear */
@@ -91,12 +78,12 @@
 #define PORT_IRQ_PIOS_FIS      (1 << 1) /* PIO Setup FIS rx'd */
 #define PORT_IRQ_D2H_REG_FIS   (1 << 0) /* D2H Register FIS rx'd */
 
-#define PORT_IRQ_FATAL         PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR     \
+#define PORT_IRQ_FATAL         PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR     \
                                | PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_ERR
 
-#define DEF_PORT_IRQ           PORT_IRQ_FATAL | PORT_IRQ_PHYRDY        \
-                               | PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE   \
-                               | PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS   \
+#define DEF_PORT_IRQ           PORT_IRQ_FATAL | PORT_IRQ_PHYRDY        \
+                               | PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE   \
+                               | PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS   \
                                | PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS \
                                | PORT_IRQ_D2H_REG_FIS
 
@@ -172,7 +159,7 @@ struct ahci_ioports {
 };
 
 struct ahci_probe_ent {
-       pci_dev_t       dev;
+       pci_dev_t       dev;
        struct ahci_ioports     port[AHCI_MAX_PORTS];
        u32     n_ports;
        u32     hard_port_no;
@@ -187,4 +174,6 @@ struct ahci_probe_ent {
        u32     link_port_map; /*linkup port map*/
 };
 
+int ahci_init(u32 base);
+
 #endif