Merge branch 'master' of git://git.denx.de/u-boot-arm into master

[karo-tx-uboot.git] / include / altera.h

diff --git a/include/altera.h b/include/altera.h
index 7a2bece03215604e65564e2ca3185c9a48824272..0327a1b82a446514b5357665cae7d3dc6315b836 100644 (file)
--- a/include/altera.h
+++ b/include/altera.h
@@ -2,24 +2,7 @@
  * (C) Copyright 2002
  * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <fpga.h>
@@ -27,23 +10,6 @@
 #ifndef _ALTERA_H_
 #define _ALTERA_H_
 
-/* Altera Model definitions
- *********************************************************************/
-#define CONFIG_SYS_ACEX1K              CONFIG_SYS_FPGA_DEV( 0x1 )
-#define CONFIG_SYS_CYCLON2             CONFIG_SYS_FPGA_DEV( 0x2 )
-#define CONFIG_SYS_STRATIX_II          CONFIG_SYS_FPGA_DEV( 0x4 )
-
-#define CONFIG_SYS_ALTERA_ACEX1K       (CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_ACEX1K)
-#define CONFIG_SYS_ALTERA_CYCLON2      (CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_CYCLON2)
-#define CONFIG_SYS_ALTERA_STRATIX_II   (CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_STRATIX_II)
-/* Add new models here */
-
-/* Altera Interface definitions
- *********************************************************************/
-#define CONFIG_SYS_ALTERA_IF_PS        CONFIG_SYS_FPGA_IF( 0x1 )       /* passive serial */
-#define CONFIG_SYS_ALTERA_IF_FPP       CONFIG_SYS_FPGA_IF( 0x2 )       /* fast passive parallel */
-/* Add new interfaces here */
-
 typedef enum {                         /* typedef Altera_iface */
        min_altera_iface_type,          /* insert all new types after this */
        passive_serial,                 /* serial data and external clock */