karo: fdt: fix panel-dpi support

[karo-tx-uboot.git] / include / configs / T208xRDB.h

diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 626b5626a943ed44d341de7f0914e25462226174..b0d8399fdd327ea6af443780329037d2e6756fe8 100644 (file)
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -11,10 +11,11 @@
 #ifndef __T2080RDB_H
 #define __T2080RDB_H
 
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_T2080RDB
 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
 #define CONFIG_MMC
-#define CONFIG_SPI_FLASH
 #define CONFIG_USB_EHCI
 #define CONFIG_FSL_SATA_V2
 
@@ -35,6 +36,7 @@
 #define CONFIG_SYS_FSL_CPC     /* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC     CONFIG_NUM_DDR_CONTROLLERS
 #define CONFIG_FSL_IFC         /* Enable IFC Support */
+#define CONFIG_FSL_CAAM                /* Enable SEC/CAAM */
 #define CONFIG_FSL_LAW         /* Use common FSL init code */
 #define CONFIG_ENV_OVERWRITE
 
@@ -42,7 +44,6 @@
 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg
 
-#define CONFIG_SPL
 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
 #define CONFIG_SPL_ENV_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
@@ -138,6 +139,11 @@
 #define CONFIG_MEM_INIT_VALUE          0xdeadbeef
 #endif
 
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START       0x00200000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END         0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+
 #ifndef CONFIG_SYS_NO_FLASH
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
@@ -283,7 +289,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS2_FTIM1           (FTIM1_GPCM_TACO(0x0e) | \
                                        FTIM1_GPCM_TRAD(0x1f))
 #define CONFIG_SYS_CS2_FTIM2           (FTIM2_GPCM_TCS(0x0e) | \
-                                       FTIM2_GPCM_TCH(0x0) | \
+                                       FTIM2_GPCM_TCH(0x8) | \
                                        FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS2_FTIM3           0x0
 
@@ -326,7 +332,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_NAND_DDR_LAW                11
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
 #define CONFIG_CMD_NAND
 #define CONFIG_SYS_NAND_BLOCK_SIZE     (512 * 1024)
 
@@ -447,6 +452,17 @@ unsigned long get_board_ddr_clk(void);
 #define I2C_MUX_PCA_ADDR_SEC2  0x76 /* I2C bus multiplexer,secondary 2 */
 #define I2C_MUX_CH_DEFAULT     0x8
 
+#define I2C_MUX_CH_VOL_MONITOR 0xa
+
+#define CONFIG_VID_FLS_ENV             "t208xrdb_vdd_mv"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_VID
+#endif
+#define CONFIG_VOL_MONITOR_IR36021_SET
+#define CONFIG_VOL_MONITOR_IR36021_READ
+/* The lowest and highest voltage allowed for T208xRDB */
+#define VDD_MV_MIN                     819
+#define VDD_MV_MAX                     1212
 
 /*
  * RapidIO
@@ -461,15 +477,15 @@ unsigned long get_board_ddr_clk(void);
  * for slave u-boot IMAGE instored in master memory space,
  * PHYS must be aligned based on the SIZE
  */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x80000 /* 512K */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 /*
  * for slave UCODE and ENV instored in master memory space,
  * PHYS must be aligned based on the SIZE
  */
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000        /* 256K */
 
@@ -551,8 +567,6 @@ unsigned long get_board_ddr_clk(void);
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata LSZ ADD */
-#define CONFIG_NET_MULTI
-#define CONFIG_E1000
 #define CONFIG_PCI_PNP         /* do pci plug-and-play */
 #define CONFIG_PCI_SCAN_SHOW   /* show pci devices on startup */
 #define CONFIG_DOS_PARTITION
@@ -565,10 +579,26 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_BMAN_MEM_BASE       0xf4000000
 #define CONFIG_SYS_BMAN_MEM_PHYS       0xff4000000ull
 #define CONFIG_SYS_BMAN_MEM_SIZE       0x02000000
+#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
+                                       CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG   0xE08
 #define CONFIG_SYS_QMAN_NUM_PORTALS    18
 #define CONFIG_SYS_QMAN_MEM_BASE       0xf6000000
 #define CONFIG_SYS_QMAN_MEM_PHYS       0xff6000000ull
 #define CONFIG_SYS_QMAN_MEM_SIZE       0x02000000
+#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
+                                       CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG   0xE08
 
 #define CONFIG_SYS_DPAA_FMAN
 #define CONFIG_SYS_DPAA_PME
@@ -629,8 +659,8 @@ unsigned long get_board_ddr_clk(void);
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define CONFIG_FMAN_ENET
 #define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_AQUANTIA
 #define CONFIG_PHY_CORTINA
-#define CONFIG_PHY_AQ1202
 #define CONFIG_PHY_REALTEK
 #define CONFIG_CORTINA_FW_LENGTH       0x40000
 #define RGMII_PHY1_ADDR                0x01  /* RealTek RTL8211E */
@@ -717,22 +747,22 @@ unsigned long get_board_ddr_clk(void);
 /*
  * Command line configuration.
  */
-#include <config_cmd_default.h>
-
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_ERRATA
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_PING
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_SETEXPR
 #define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_BDI
 
 #ifdef CONFIG_PCI
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_NET
+#endif
+
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
 #endif
 
 /*
@@ -742,7 +772,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMDLINE_EDITING         /* Command-line editing */
 #define CONFIG_AUTO_COMPLETE           /* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR   0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT      "=> "     /* Monitor Command Prompt */
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_SYS_CBSIZE      1024      /* Console I/O Buffer Size */
 #else
@@ -867,6 +896,7 @@ unsigned long get_board_ddr_clk(void);
 
 #ifdef CONFIG_SECURE_BOOT
 #include <asm/fsl_secure_boot.h>
+#define CONFIG_CMD_BLOB
 #undef CONFIG_CMD_USB
 #endif