[PPC440SPe] PCIe environment settings for Katmai and Yucca

[karo-tx-uboot.git] / include / configs / katmai.h

diff --git a/include/configs/katmai.h b/include/configs/katmai.h
index e6ebe3815d67e7211595153d07ea7bddd421faab..7908e5a4743b2a23bbe84fc735d4d97bc7588114 100644 (file)
--- a/include/configs/katmai.h
+++ b/include/configs/katmai.h
@@ -29,7 +29,7 @@
 
 #ifndef __CONFIG_H
 #define __CONFIG_H
-//#define DEBUG
+
 /*-----------------------------------------------------------------------
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
@@ -42,7 +42,6 @@
 
 #define CONFIG_BOARD_EARLY_INIT_F 1    /* Call board_pre_init          */
 #define        CONFIG_MISC_INIT_F      1       /* Use misc_init_f()            */
-#define CONFIG_ADD_RAM_INFO    1       /* Print additional info        */
 #undef  CONFIG_SHOW_BOOT_PROGRESS
 
 /*-----------------------------------------------------------------------
@@ -67,11 +66,11 @@
 #define CFG_PCIE_BASE          0xe0000000      /* PCIe UTL regs */
 
 #define CFG_PCIE0_CFGBASE      0xc0000000
-#define CFG_PCIE0_XCFGBASE     0xc0000400
-#define CFG_PCIE1_CFGBASE      0xc0001000
-#define CFG_PCIE1_XCFGBASE     0xc0001400
-#define CFG_PCIE2_CFGBASE      0xc0002000
-#define CFG_PCIE2_XCFGBASE     0xc0002400
+#define CFG_PCIE1_CFGBASE      0xc1000000
+#define CFG_PCIE2_CFGBASE      0xc2000000
+#define CFG_PCIE0_XCFGBASE     0xc3000000
+#define CFG_PCIE1_XCFGBASE     0xc3001000
+#define CFG_PCIE2_XCFGBASE     0xc3002000
 
 /* System RAM mapped to PCI space */
 #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
@@ -202,6 +201,7 @@
                "setenv filesize;saveenv\0"                             \
        "upd=run load;run update\0"                                     \
        "kozio=bootm ffc60000\0"                                        \
+       "pciconfighost=1\0"                                             \
        ""
 #define CONFIG_BOOTCOMMAND     "run flash_self"
 
@@ -210,28 +210,40 @@
 #define CONFIG_LOADS_ECHO      1       /* echo on for serial download  */
 #define CFG_LOADS_BAUD_CHANGE  1       /* allow baudrate change        */
 
-#define CONFIG_COMMANDS               (CONFIG_CMD_DFL  | \
-                               CFG_CMD_ASKENV  | \
-                               CFG_CMD_EEPROM  | \
-                               CFG_CMD_DATE    | \
-                               CFG_CMD_DHCP    | \
-                               CFG_CMD_DIAG    | \
-                               CFG_CMD_DTT     | \
-                               CFG_CMD_ELF     | \
-                               CFG_CMD_EXT2    | \
-                               CFG_CMD_FAT     | \
-                               CFG_CMD_I2C     | \
-                               CFG_CMD_IRQ     | \
-                               CFG_CMD_MII     | \
-                               CFG_CMD_NET     | \
-                               CFG_CMD_NFS     | \
-                               CFG_CMD_PCI     | \
-                               CFG_CMD_PING    | \
-                               CFG_CMD_REGINFO | \
-                               CFG_CMD_SDRAM)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+
 
 #define        CONFIG_IBM_EMAC4_V4     1       /* 440SPe has this EMAC version */
 #define CONFIG_MII             1       /* MII PHY management           */
@@ -254,7 +266,7 @@
 #define CFG_LONGHELP                           /* undef to save memory         */
 #define CFG_PROMPT             "=> "           /* Monitor Command Prompt       */
 
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define CFG_CBSIZE             1024            /* Console I/O Buffer Size      */
 #else
 #define CFG_CBSIZE             256             /* Console I/O Buffer Size      */
@@ -311,10 +323,9 @@
 #define CONFIG_PCI                     /* include pci support          */
 #define CONFIG_PCI_PNP         1       /* do pci plug-and-play         */
 #define CONFIG_PCI_SCAN_SHOW   1       /* show pci devices on startup  */
-#undef CONFIG_PCI_CONFIG_HOST_BRIDGE
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
 
 /* Board-specific PCI */
-#define CFG_PCI_PRE_INIT       1       /* enable board pci_pre_init()  */
 #define CFG_PCI_TARGET_INIT            /* let board init pci target    */
 #undef CFG_PCI_MASTER_INIT
 
@@ -421,7 +432,7 @@
  */
 #define CFG_DCACHE_SIZE                8192    /* For AMCC 405 CPUs            */
 #define CFG_CACHELINE_SIZE     32      /* ...                          */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 #endif
 
@@ -433,7 +444,7 @@
 #define BOOTFLAG_COLD  0x01            /* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM  0x02            /* Software reboot */
 
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE   230400  /* speed to run kgdb serial port */
 #define CONFIG_KGDB_SER_INDEX  2       /* which serial port to use */
 #endif