Move defaults from config_cmd_default.h to Kconfig

[karo-tx-uboot.git] / include / configs / ls1021atwr.h

diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 972becd9a41cd58bc3b3630633f7012d9eb5a5d6..d58939758aebe56052c80a5a02bb2d7288ac0c02 100644 (file)
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -7,9 +7,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#include <config_cmd_default.h>
-
-#define CONFIG_LS102XA
 
 #define CONFIG_SYS_GENERIC_BOARD
 
@@ -35,6 +32,29 @@
 #define CONFIG_SYS_CLK_FREQ            100000000
 #define CONFIG_DDR_CLK_FREQ            100000000
 
+#define DDR_SDRAM_CFG                  0x470c0008
+#define DDR_CS0_BNDS                   0x008000bf
+#define DDR_CS0_CONFIG                 0x80014302
+#define DDR_TIMING_CFG_0               0x50550004
+#define DDR_TIMING_CFG_1               0xbcb38c56
+#define DDR_TIMING_CFG_2               0x0040d120
+#define DDR_TIMING_CFG_3               0x010e1000
+#define DDR_TIMING_CFG_4               0x00000001
+#define DDR_TIMING_CFG_5               0x03401400
+#define DDR_SDRAM_CFG_2                        0x00401010
+#define DDR_SDRAM_MODE                 0x00061c60
+#define DDR_SDRAM_MODE_2               0x00180000
+#define DDR_SDRAM_INTERVAL             0x18600618
+#define DDR_DDR_WRLVL_CNTL             0x8655f605
+#define DDR_DDR_WRLVL_CNTL_2           0x05060607
+#define DDR_DDR_WRLVL_CNTL_3           0x05050505
+#define DDR_DDR_CDR1                   0x80040000
+#define DDR_DDR_CDR2                   0x00000001
+#define DDR_SDRAM_CLK_CNTL             0x02000000
+#define DDR_DDR_ZQ_CNTL                        0x89080600
+#define DDR_CS0_CONFIG_2               0
+#define DDR_SDRAM_CFG_MEM_EN           0x80000000
+
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
 #endif
@@ -67,8 +87,13 @@
 #define CONFIG_SYS_MONITOR_LEN         0x80000
 #endif
 
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_SYS_TEXT_BASE           0x40010000
+#define CONFIG_SYS_NO_FLASH
+#endif
+
 #ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE           0x67f80000
+#define CONFIG_SYS_TEXT_BASE           0x60100000
 #endif
 
 #define CONFIG_NR_DRAM_BANKS           1
@@ -90,6 +115,7 @@
 /*
  * IFC Definitions
  */
+#ifndef CONFIG_QSPI_BOOT
 #define CONFIG_FSL_IFC
 #define CONFIG_SYS_FLASH_BASE          0x60000000
 #define CONFIG_SYS_FLASH_BASE_PHYS     CONFIG_SYS_FLASH_BASE
@@ -133,6 +159,7 @@
 
 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 #define CONFIG_SYS_WRITE_SWAPPED_DATA
+#endif
 
 /* CPLD */
 
@@ -179,11 +206,16 @@
 /*
  * Serial Port
  */
+#ifdef CONFIG_LPUART
+#define CONFIG_FSL_LPUART
+#define CONFIG_LPUART_32B_REG
+#else
 #define CONFIG_CONS_INDEX              1
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE    1
 #define CONFIG_SYS_NS16550_CLK         get_serial_clock()
+#endif
 
 #define CONFIG_BAUDRATE                        115200
 
@@ -193,6 +225,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 
 /* EEPROM */
 #ifndef CONFIG_SD_BOOT
@@ -216,6 +249,17 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
+/* QSPI */
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_FSL_QSPI
+#define QSPI0_AMBA_BASE                        0x40000000
+#define FSL_QSPI_FLASH_SIZE            (1 << 24)
+#define FSL_QSPI_FLASH_NUM             2
+
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_STMICRO
+#endif
+
 /*
  * Video
  */
@@ -279,25 +323,59 @@
 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
 
+#define CONFIG_SYS_PCI_64BIT
+
+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF  0x00000000
+#define CONFIG_SYS_PCIE_CFG0_SIZE      0x00001000      /* 4k */
+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF  0x00001000
+#define CONFIG_SYS_PCIE_CFG1_SIZE      0x00001000      /* 4k */
+
+#define CONFIG_SYS_PCIE_IO_BUS         0x00000000
+#define CONFIG_SYS_PCIE_IO_PHYS_OFF    0x00010000
+#define CONFIG_SYS_PCIE_IO_SIZE                0x00010000      /* 64k */
+
+#define CONFIG_SYS_PCIE_MEM_BUS                0x08000000
+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF   0x04000000
+#define CONFIG_SYS_PCIE_MEM_SIZE       0x08000000      /* 128M */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_E1000
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+#endif
+
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
 
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_CMDLINE_EDITING
 
-#define CONFIG_CMD_IMLS
+#define CONFIG_ARMV7_NONSEC
+#define CONFIG_ARMV7_VIRT
+#define CONFIG_PEN_ADDR_BIG_ENDIAN
+#define CONFIG_LS102XA_NS_ACCESS
+#define CONFIG_SMP_PEN_ADDR            0x01ee0200
+#define CONFIG_TIMER_CLK_FREQ          12500000
+#define CONFIG_ARMV7_SECURE_BASE       OCRAM_BASE_S_ADDR
 
 #define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE           128
 
 #define CONFIG_BOOTDELAY               3
 
+#ifdef CONFIG_LPUART
+#define CONFIG_EXTRA_ENV_SETTINGS       \
+       "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
+       "initrd_high=0xcfffffff\0"      \
+       "fdt_high=0xcfffffff\0"
+#else
 #define CONFIG_EXTRA_ENV_SETTINGS      \
        "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
        "initrd_high=0xcfffffff\0"      \
        "fdt_high=0xcfffffff\0"
+#endif
 
 /*
  * Miscellaneous configurable options
@@ -312,7 +390,6 @@
 #define CONFIG_SYS_MAXARGS             16      /* max number of command args */
 #define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE
 
-#define CONFIG_CMD_ENV_EXISTS
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_MEMINFO
 #define CONFIG_CMD_MEMTEST
@@ -321,6 +398,8 @@
 
 #define CONFIG_SYS_LOAD_ADDR           0x82000000
 
+#define CONFIG_LS102XA_STREAM_ID
+
 /*
  * Stack sizes
  * The stack sizes are set up in start.S using the settings below
@@ -350,6 +429,11 @@
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV         0
 #define CONFIG_ENV_SIZE                        0x20000
+#elif defined(CONFIG_QSPI_BOOT)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE                        0x2000
+#define CONFIG_ENV_OFFSET              0x100000
+#define CONFIG_ENV_SECT_SIZE           0x10000
 #else
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_ADDR                (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)