ppc4xx: Fix SDRAM inititialization of multiple 405 based board ports

[karo-tx-uboot.git] / include / configs / quad100hd.h

diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h
index 622a5d4cccdc7f54e64450f95d5aaa179e164362..c41f5c948718e6cb62f6a1557363d465b686ed57 100644 (file)
--- a/include/configs/quad100hd.h
+++ b/include/configs/quad100hd.h
@@ -82,7 +82,6 @@
  * SDRAM configuration (please see cpu/ppc/sdram.[ch])
  */
 #define CONFIG_SDRAM_BANK0  1
-#define CFG_SDRAM_SIZE      0x02000000      /* 32 MB */
 
 /* FIX! SDRAM timings used in datasheet */
 #define CFG_SDRAM_CL            3       /* CAS latency */
@@ -182,7 +181,7 @@
  * FLASH organization
  */
 #define CFG_FLASH_CFI                  /* The flash is CFI compatible  */
-#define        CFG_FLASH_CFI_DRIVER
+#define        CONFIG_FLASH_CFI_DRIVER
 
 #define CFG_FLASH_BANKS_LIST   { CFG_FLASH_BASE }