*/
#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
-/*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */
-
/* Environment information, boards can override if required */
#define CONFIG_LOADADDR 0x00408000 /* def. location for kernel */