Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx

[karo-tx-uboot.git] / include / mpc83xx.h

diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 191488aa89938d2454438bdd36878b717435c9e3..44115c91b410daeaa325bd8186447b169e72b112 100644 (file)
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -54,7 +54,7 @@
 #define SPRIDR_PARTID                  0xFFFF0000      /* Part Id */
 #define SPRIDR_REVID                   0x0000FFFF      /* Revision Id */
 
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834x)
 #define REVID_MAJOR(spridr)            ((spridr & 0x0000FF00) >> 8)
 #define REVID_MINOR(spridr)            (spridr & 0x000000FF)
 #else
@@ -100,7 +100,7 @@
 #define SPCR_COREPR                    0x00300000      /* E300 PowerPC Core system bus request priority */
 #define SPCR_COREPR_SHIFT              (31-11)
 
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834x)
 /* SPCR bits - MPC8349 specific */
 #define SPCR_TSEC1DP                   0x00003000      /* TSEC1 data priority */
 #define SPCR_TSEC1DP_SHIFT             (31-19)
@@ -115,7 +115,7 @@
 #define SPCR_TSEC2EP                   0x00000003      /* TSEC2 emergency priority */
 #define SPCR_TSEC2EP_SHIFT             (31-31)
 
-#elif defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
+#elif defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
 /* SPCR bits - MPC831x and MPC837x specific */
 #define SPCR_TSECDP                    0x00003000      /* TSEC data priority */
 #define SPCR_TSECDP_SHIFT              (31-19)
@@ -127,7 +127,7 @@
 
 /* SICRL/H - System I/O Configuration Register Low/High
  */
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834x)
 /* SICRL bits - MPC8349 specific */
 #define SICRL_LDP_A                    0x80000000
 #define SICRL_USB1                     0x40000000
@@ -190,8 +190,8 @@
 #define SICRH_UC2E1OBI                 0x00000002
 #define SICRH_UC2E2OBI                 0x00000001
 
-#elif defined(CONFIG_MPC832X)
-/* SICRL bits - MPC832X specific */
+#elif defined(CONFIG_MPC832x)
+/* SICRL bits - MPC832x specific */
 #define SICRL_LDP_LCS_A                        0x80000000
 #define SICRL_IRQ_CKS                  0x20000000
 #define SICRL_PCI_MSRC                 0x10000000
@@ -262,10 +262,11 @@
 #define SICRH_TSOBI1                   0x00000002
 #define SICRH_TSOBI2                   0x00000001
 
-#elif defined(CONFIG_MPC837X)
+#elif defined(CONFIG_MPC837x)
 /* SICRL bits - MPC837x specific */
 #define SICRL_USB_A                    0xC0000000
 #define SICRL_USB_B                    0x30000000
+#define SICRL_USB_B_SD                 0x20000000
 #define SICRL_UART                     0x0C000000
 #define SICRL_GPIO_A                   0x02000000
 #define SICRL_GPIO_B                   0x01000000
@@ -307,10 +308,12 @@
 #define SICRH_GPIO2_C                  0x00002000
 #define SICRH_GPIO2_D                  0x00001000
 #define SICRH_GPIO2_E                  0x00000C00
+#define SICRH_GPIO2_E_SD               0x00000800
 #define SICRH_GPIO2_F                  0x00000300
 #define SICRH_GPIO2_G                  0x000000C0
 #define SICRH_GPIO2_H                  0x00000030
 #define SICRH_SPI                      0x00000003
+#define SICRH_SPI_SD                   0x00000001
 #endif
 
 /* SWCRR - System Watchdog Control Register
@@ -421,7 +424,7 @@
 #define HRCWL_CORE_TO_CSB_2_5X1                0x00050000
 #define HRCWL_CORE_TO_CSB_3X1          0x00060000
 
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
 #define HRCWL_CEVCOD                   0x000000C0
 #define HRCWL_CEVCOD_SHIFT             6
 #define HRCWL_CE_PLL_VCO_DIV_4         0x00000000
@@ -475,7 +478,7 @@
 #define HRCWL_SVCOD_DIV_8              0x20000000
 #define HRCWL_SVCOD_DIV_1              0x30000000
 
-#elif defined(CONFIG_MPC837X)
+#elif defined(CONFIG_MPC837x)
 #define HRCWL_SVCOD                    0x30000000
 #define HRCWL_SVCOD_SHIFT              28
 #define HRCWL_SVCOD_DIV_4              0x00000000
@@ -490,7 +493,7 @@
 #define HRCWH_PCI_HOST_SHIFT           31
 #define HRCWH_PCI_AGENT                        0x00000000
 
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834x)
 #define HRCWH_32_BIT_PCI               0x00000000
 #define HRCWH_64_BIT_PCI               0x40000000
 #endif
@@ -501,7 +504,7 @@
 #define HRCWH_PCI_ARBITER_DISABLE      0x00000000
 #define HRCWH_PCI_ARBITER_ENABLE       0x20000000
 
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834x)
 #define HRCWH_PCI2_ARBITER_DISABLE     0x00000000
 #define HRCWH_PCI2_ARBITER_ENABLE      0x10000000
 
@@ -525,17 +528,17 @@
 
 #define HRCWH_ROM_LOC_DDR_SDRAM                0x00000000
 #define HRCWH_ROM_LOC_PCI1             0x00100000
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834x)
 #define HRCWH_ROM_LOC_PCI2             0x00200000
 #endif
-#if defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC837x)
 #define HRCWH_ROM_LOC_ON_CHIP_ROM      0x00300000
 #endif
 #define HRCWH_ROM_LOC_LOCAL_8BIT       0x00500000
 #define HRCWH_ROM_LOC_LOCAL_16BIT      0x00600000
 #define HRCWH_ROM_LOC_LOCAL_32BIT      0x00700000
 
-#if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
 #define HRCWH_ROM_LOC_NAND_SP_8BIT     0x00100000
 #define HRCWH_ROM_LOC_NAND_SP_16BIT    0x00200000
 #define HRCWH_ROM_LOC_NAND_LP_8BIT     0x00500000
@@ -559,7 +562,7 @@
 #define HRCWH_TSEC2M_IN_SGMII          0x00001800
 #endif
 
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834x)
 #define HRCWH_TSEC1M_IN_RGMII          0x00000000
 #define HRCWH_TSEC1M_IN_RTBI           0x00004000
 #define HRCWH_TSEC1M_IN_GMII           0x00008000
@@ -586,7 +589,7 @@
 
 /* RSR - Reset Status Register
  */
-#if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
 #define RSR_RSTSRC                     0xF0000000      /* Reset source */
 #define RSR_RSTSRC_SHIFT               28
 #else
@@ -679,7 +682,7 @@
 #define SCCR_PCICM                     0x00010000
 #define SCCR_PCICM_SHIFT               16
 
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834x)
 /* SCCR bits - MPC834x specific */
 #define SCCR_TSEC1CM                   0xc0000000
 #define SCCR_TSEC1CM_SHIFT             30
@@ -767,7 +770,7 @@
 #define SCCR_TDMCM_2                   0x00000020
 #define SCCR_TDMCM_3                   0x00000030
 
-#elif defined(CONFIG_MPC837X)
+#elif defined(CONFIG_MPC837x)
 /* SCCR bits - MPC837x specific */
 #define SCCR_TSEC1CM                   0xc0000000
 #define SCCR_TSEC1CM_SHIFT             30
@@ -834,6 +837,9 @@
 #define CSCONFIG_EN                    0x80000000
 #define CSCONFIG_AP                    0x00800000
 #define CSCONFIG_ODT_WR_ACS            0x00010000
+#if defined(CONFIG_MPC832x)
+#define CSCONFIG_ODT_WR_CFG            0x00040000
+#endif
 #define CSCONFIG_BANK_BIT_3            0x00004000
 #define CSCONFIG_ROW_BIT               0x00000700
 #define CSCONFIG_ROW_BIT_12            0x00000000
@@ -887,6 +893,8 @@
 #define TIMING_CFG1_CASLAT_30          0x00050000      /* CAS latency = 3.0 */
 #define TIMING_CFG1_CASLAT_35          0x00060000      /* CAS latency = 3.5 */
 #define TIMING_CFG1_CASLAT_40          0x00070000      /* CAS latency = 4.0 */
+#define TIMING_CFG1_CASLAT_45          0x00080000      /* CAS latency = 4.5 */
+#define TIMING_CFG1_CASLAT_50          0x00090000      /* CAS latency = 5.0 */
 
 /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
  */
@@ -1036,22 +1044,6 @@
 #define ECC_ERROR_MAN_SBEC             (0xff000000>>24)        /* Single Bit Error Counter 0..255 */
 #define ECC_ERROR_MAN_SBEC_SHIFT       0
 
-/* DMAMR - DMA Mode Register
- */
-#define DMA_CHANNEL_START                      0x00000001      /* Bit - DMAMRn CS */
-#define DMA_CHANNEL_TRANSFER_MODE_DIRECT       0x00000004      /* Bit - DMAMRn CTM */
-#define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN     0x00001000      /* Bit - DMAMRn SAHE */
-#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B     0x00000000      /* 2Bit- DMAMRn SAHTS 1byte */
-#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B     0x00004000      /* 2Bit- DMAMRn SAHTS 2bytes */
-#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B     0x00008000      /* 2Bit- DMAMRn SAHTS 4bytes */
-#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B     0x0000c000      /* 2Bit- DMAMRn SAHTS 8bytes */
-#define DMA_CHANNEL_SNOOP                      0x00010000      /* Bit - DMAMRn DMSEN */
-
-/* DMASR - DMA Status Register
- */
-#define DMA_CHANNEL_BUSY                       0x00000004      /* Bit - DMASRn CB */
-#define DMA_CHANNEL_TRANSFER_ERROR             0x00000080      /* Bit - DMASRn TE */
-
 /* CONFIG_ADDRESS - PCI Config Address Register
  */
 #define PCI_CONFIG_ADDRESS_EN          0x80000000